中图分类号：TP391 文献标志码：A DOI: 10.16157/j.issn.0258-7998.234372
中文引用格式：邱臻博. 一种基于FPGA的CNN硬件加速器实现[J]. 电子技术应用，2023，49(12)：20-25.
英文引用格式：Qiu Zhenbo. An FPGA-based implementation of CNN hardware accelerator[J]. Application of Electronic Technique，2023，49(12)：20-25.
An FPGA-based implementation of CNN hardware accelerator
Qiu Zhenbo
College of Photoelectric Engineering， Chongqing University of Posts and Telecommunications， Chongqing 400065， China
Abstract：This paper proposes a general CNN hardware accelerator design scheme based on FPGA. For the most computationally intensive convolutional layer, three acceleration modes are adopted: input channel parallelism, intra-core parallelism, and output channel parallelism, and the corresponding parallelism degree is reasonably set according to the on-chip resources of FPGA. In terms of data loading, adjacent data bit width combined transmission is adopted, which effectively improves the actual transmission bandwidth of the accelerator. Based on the idea of row-based data flow loading, the input cache module is designed. The cache module only needs to cache two rows of data to start the convolution operation, effectively advancing the start time of the convolution operation. Between the data input, data operation, and data output modules, the pipeline cycle optimization method is used to greatly improve the computing performance of the hardware. Finally, the accelerator is applied to VGG16 and Darknet-19 networks, and experiments show that the computing performance reaches 34.30 GOPS and 33.68 GOPS, respectively, and the DSP computing efficiency is as high as 79.45% and 78.01%.
Key words :convolutional neural network acceleration；FPGA；row data loading；module division；pipeline structure
