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基于PG网络的全流程优化在高性能CPU内核中的应用
2023年电子技术应用第8期
姜姝,杨超,吴驰
(上海云豹创芯智能科技有限公司,上海 201210)
摘要:随着高性能计算芯片的集成度不断提高以及工艺的进步, 金属连线的宽度越来越窄,芯片电源网络上电阻增加和高密度的逻辑门单元同时有逻辑翻转动作时会在电源网络上产生电压降(IR Drop),导致芯片产生时序问题,甚至可能发生逻辑门的功能故障。
中图分类号:TN402 文献标志码:A DOI: 10.16157/j.issn.0258-7998.239807
中文引用格式:姜姝,杨超,吴驰. 基于PG网络的全流程优化在高性能CPU内核中的应用[J]. 电子技术应用,2023,49(8):36-41.
英文引用格式:Jiang Shu,Yang Chao,Wu Chi. Application of fully automated optimization based on PG network in high performance CPU core[J]. Application of Electronic Technique,2023,49(8):36-41.
Application of fully automated optimization based on PG network in high performance CPU core
Jiang Shu,Yang Chao,Wu Chi
(Jaguar Microsystems, Shanghai 201210, China)
Abstract:With the continuous improvement of the integration of high-performance computing chips and the advancement of technology, the width of metal wires is getting narrower and narrower, and the voltage drop (IR drop) will occur on the power network when the resistance on the chip power network increases and the high-density logic gate unit has a logic flip action at the same time, resulting in timing problems in the chip, and even the functional failure of the logic gate may occur. Based on the flash PG flow of the Cadence implementation tool Innovus, this paper completes the comprehensive implementation and rapid iteration of the PG network, and uses auto reinforce PG and trim PG to realize the trade-off between the voltage drop and timing of the high-performance CPU core from two aspects, and completes the whole process optimization of the PG network from floorplan to PR (Placement and Route) stage. The results show that under the premise of the same machine resources, flash PG flow can increase the speed of powerplan up to 10 times the original, especially in the design of the top level, which can effectively save the exploration time of PG mesh in the early stage of design. Auto reinforce PG and trim PG repair 66% of the dynamic IR drop violations by reinforcing the PG of the weak IR area and trimming the redundant PG respectively, and at the same time provide more winding resources for the design to achieve the purpose of not deteriorating the timing and DRC (Design Rule Check).
Key words :chip design;flasg PG;IR drop fixing

0 引言

随着高性能计算芯片的集成度不断提高以及工艺的进步,加上逻辑电路与电源网络的复杂程度也越来越高,芯片中某些区域会出现局部电流较大的现象,使得所在区域电压降 (IR Drop)增大,导致逻辑单元上的实际工作电压低于理想工作电压,导致芯片产生时序问题,甚至可能发生逻辑门的功能故障[1-4]。本文基于Cadence实现工具Innovus的flash PG flow完成对于PG 网络的综合实现与快速迭代,并利用 auto reinforce PG和trim PG从两方面实现了对高性能CPU核的电压降与时序之间的trade-off,完成从布图规划(floorplan)阶段到PR(Placement and Route)阶段针对PG网络的流程优化。



本文详细内容请下载:http://www.chinaaet.com/resource/share/2000005478




作者信息:

姜姝,杨超,吴驰

(上海云豹创芯智能科技有限公司,上海 201210)


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