TI公司的TMS320C6655/57是不定点/浮点数字信号处理器(DSP),基于KeyStone多核架构,内核速度高达1.25GHz,集成了各种包括C66x内核,存储器子系统,外设和加速器在内的各种子系统,非常适用于高性能低功耗可编程应用，如任务关键型,测试与自动化,医疗影像以及基础设施设备等领域.本文介绍了TMS320C6655/57主要特性,框图以及C6657 Lite EVM评估板TMDXEVM6657L主要特性,方框图,电路图,PCB元件布局图和材料清单.

The TMS320C6655/57 DSP is a highest-performance fixed/floating-point DSP that is based on TI’s KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 1.25 GHz. For developers of a broad range of applications, such as mission critical, medical imaging, test and automation, and other applications requiring high performance, TI’s TMS320C6655/57 DSP offers up to 2.5 GHz cumulative DSP and enables a platform that is power-efficient and easy to use. In addition, it is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intra-device and inter-device communication that allows the various DSP resources to operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a non-blocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating point capability and the per core raw computational performance is an industry-leading 40 GMACS/core and 20 GFLOPS/core (@1.25 GHz operating frequency). It can execute 8 single precision floating point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backwards code compatible with TI’s previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C6655/57 DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, there is 1024KB of dedicated memory per core that can be configured as mapped RAM or cache. The device also integrates 1024KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at 1333 MHz and has ECC DRAM support.

This family supports a number of high speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and Gigabit Ethernet. It also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port, and a 16-bit asynchronous EMIF, along with general purpose CMOS IO. For high throughput, low latency communication between devices or with an FPGA, a 40-Gbaud full-duplex interface called HyperLink is included.

The C6655/57 device has a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a WindowsR debugger interface for visibility into source code execution.

TMS320C6655/57主要特性:

• One (C6655) or Two (C6657) TMS320C66x™ DSP Core Subsystems (CorePacs), Each With
– 850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz C66x Fixed/Floating-Point CPU Core
› 40 GMAC/Core for Fixed Point @ 1.25 GHz
› 20 GFLOP/Core for Floating Point @ 1.25 GHz
– Memory
› 32K Byte L1P Per Core
› 32K Byte L1D Per Core
› 1024K Byte Local L2 Per Core
• Multicore Shared Memory Controller (MSMC)
– 1024KB MSM SRAM Memory (Shared by Two DSP C66x CorePacs for C6657)
– Memory Protection Unit for Both MSM SRAM and DDR3_EMIF
• Multicore Navigator
– 8192 Multipurpose Hardware Queues with Queue Manager
– Packet-Based DMA for Zero-Overhead Transfers
• Hardware Accelerators
– Two Viterbi Coprocessors
– One Turbo Coprocessor Decoder
• Peripherals
– Four Lanes of SRIO 2.1
› 1.24/2.5/3.125/5 GBaud Operation Supported Per Lane
› Supports Direct I/O, Message Passing
› Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations
– PCIe Gen2
› Single Port Supporting 1 or 2 Lanes
› Supports Up To 5 GBaud Per Lane
– HyperLink
› Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability
› Supports up to 40 Gbaud
– Gigabit Ethernet (GbE) Subsystem
› One SGMII Port
› Supports 10/100/1000 Mbps Operation
– 32-Bit DDR3 Interface
› DDR3-1333
› 8G Byte Addressable Memory Space
– 16-Bit EMIF
– Universal Parallel Port
› Two Channels of 8 bits or 16 bits Each
› Supports SDR and DDR Transfers
– Two UART Interfaces
– Two Multichannel Buffered Serial Ports (McBSP)
– I2C Interface
– 32 GPIO Pins
– SPI Interface
– Semaphore Module
– Eight 64-Bit Timers
– Two On-Chip PLLs
– SoC Security Support
• Commercial Temperature:
– 0℃ to 85℃
• Extended Temperature:
– - 40℃ to 100℃
• Extended Low Temperature:
– - 55℃ to 100℃

图1.TMS320C6655/57框图
C6657 Lite EVM评估板TMDXEVM6657L

The C6657 Lite EVM is a high performance, cost-efficient, standalone development platform that enables users to evaluate and develop applications for the Texas Instruments‟TMS320C6657Digital Signal Processor (DSP). The Evaluation Module (EVM) also serves as a hardware reference design platform for the TMS320C6657 DSP. The EVM‟s form-factor is equivalent to a single-wide PICMG® AMC.0 R2.0 AdvancedMC module. TMDSEVM6657LE comes with an integrated, high speed, system trace capable XDS560v2 Mezzanine Emulator. TMDSEVM6657LS comes with an integrated, high speed, XDS200 Mezzanine Emulator. Schematics, code examples and application notes are available, to ease the hardware development process and to reduce the time to market.

评估板TMDXEVM6657L主要特性:

 Texas Instruments’ fixed point DSP - TMS320C6657
 512 Mbytes of DDR3 Memory (up to 1024Mbytes supported)
 128 Mbytes of NAND Flash
 16 Mbytes of NOR Flash
 One Gigabit Ethernet port supporting 10/100/1000 Mbps data rate – switched between RJ-45 connector and AMC fingers
 170 pin B+ style AMC Interface
 High performance connector for HyperLink
 128 kbytes I2C EEPROM for booting
 4 User Indication LEDs, 4 Software Controlled LEDs and 3 User DIP Switches
 RS232 Serial interface on 3-Pin header or UART over mini-USB connector
 UPP, Timer, SPI, McBSP, UART interfaces on 80-pin expansion header
 On-Board XDS100 type Emulation using USB 2.0 interface
 TI 60-Pin JTAG header to support External Emulator[1]
 High Speed Integrated XDS560v2 Mezzanine Emulator[2]
 High Speed Integrated XDS200 Mezzanine Emulator[3]
 Module Management Controller (MMC) for Intelligent Platform Management Interface (IPMI)
 Powered by DC power-brick adaptor (12V/2.5A) or AMC Carrier back-plane
 PICMG® AMC.0 R2.0 single width, full height AdvancedMC module

The C6657 Lite EVM contains dual TMS320C6657 fixed point Digital Signal Processor. The TMS320C6657 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture, developed by Texas Instruments (TI), designed specifically for high density wireline / wireless media gateway infrastructure. This device is an excellent choice for IP border gateways, video transcoding and translation, video-server and intelligent voice and video recognition applications. The C66x devices are backward code-compatible from previous devices that are part of the C6000™ DSP platform.

图2. 评估板TMDXEVM6657L框图

图3. TMDXEVM6657L外形图

图4. 评估板TMDXEVM6657L框图

图5.评估板TMDXEVM6657L元件布局图

图6.评估板TMDXEVM6657L功耗图

图7.评估板TMDXEVM6657L功耗分布图

图8.评估板TMDXEVM6657L时钟图

图9.评估板TMDXEVM6657L电路图(1)

图10.评估板TMDXEVM6657L电路图(2)

图11.评估板TMDXEVM6657L电路图(3)

图12.评估板TMDXEVM6657L电路图(4)

图13.评估板TMDXEVM6657L电路图(5)

图14.评估板TMDXEVM6657L电路图(6)

图15.评估板TMDXEVM6657L电路图(7)

图16.评估板TMDXEVM6657L电路图(8)

图17.评估板TMDXEVM6657L电路图(9)

图18.评估板TMDXEVM6657L电路图(10)

图19.评估板TMDXEVM6657L电路图(11)

图20.评估板TMDXEVM6657L电路图(12)

图21.评估板TMDXEVM6657L电路图(13)

图22.评估板TMDXEVM6657L电路图(14)

图23.评估板TMDXEVM6657L电路图(15)

图24.评估板TMDXEVM6657L电路图(16)

图25.评估板TMDXEVM6657L电路图(17)

图26.评估板TMDXEVM6657L电路图(18)

图27.评估板TMDXEVM6657L电路图(19)

图28.评估板TMDXEVM6657L电路图(20)

图29.评估板TMDXEVM6657L PCB元件布局图:顶层

图30.评估板TMDXEVM6657L PCB元件布局图:底层