晚上闲来无事，拿出ZED，研究了下硬件说明手册，调了几个跳线，然后写了一个LED 代码，verilog 的，然后漫长的编译配置，烧写进去，哈哈，结果好了，然后我赶紧写了一个VGA 的驱动，放进去，编译配置，烧写进去，VGA 也可以显示了，

哈哈，注明以上均为verilog 逻辑代码，没用ARM，还是FPGA 用起来直接，

LED 源码我就不上了，免得被K，VGA 代码附上，

其工程新建什么的，跟ISE12版本类似，不多说了，代码附上可以自己实践，其中跳线设置：拔掉MIO3,4,5,6，把MIO2=0，其他的不动。

//////////////////////////////////////////////////////////////////////////////////
module test
(
sys_clk,out, //CLK =100M
hsync,vsync,
vga_r,vga_g,vga_b
);

input sys_clk;
output out;

// input rst_n; //低电平复位
output hsync; //行同步信号
output vsync; //场同步信号
output vga_r; //红基色信号
output vga_g; //绿基色信号
output vga_b; //蓝基色信号

wire vsync,hsync;
wire vga_r,vga_g,vga_b;

reg out;
reg [31:0] count;

wire rst_n;
assign rst_n = 1'b1;
//==========================================================
// 测试LED
//==========================================================
always @ ( posedge sys_clk or negedge rst_n )
begin
if( !rst_n )
begin
out <= 1'b0;
count <= 32'd0;
end
else if( count== 32'd50000000)
begin
out <= ~out;
count <= 32'd0;
end
else
begin
count<=count+1'b1;
end
end
//==========================================================
// 产生 VGA clk 50M
//==========================================================
reg clk;
always @ ( posedge sys_clk )
begin
clk = ~ clk;
end

//==========================================================
// 定义行列坐标以及数据
//==========================================================
reg[10:0] x_cnt; //行坐标
reg[9:0] y_cnt; //列坐标

always @ (posedge clk or negedge rst_n)
begin
if(!rst_n) x_cnt <= 11'd0;
else if(x_cnt == 11'd1039) x_cnt <= 11'd0;
else x_cnt <= x_cnt+1'b1;
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n) y_cnt <= 10'd0;
else if(y_cnt == 10'd665) y_cnt <= 10'd0;
else if(x_cnt == 11'd1039) y_cnt <= y_cnt+1'b1;
end
//--------------------------------------------------
wire valid; //有效显示区标志

assign valid = (x_cnt >= 11'd187) && (x_cnt < 11'd987)
&& (y_cnt >= 10'd31) && (y_cnt < 10'd631);

wire[9:0] xpos,ypos; //有效显示区坐标

assign xpos = x_cnt-11'd187;
assign ypos = y_cnt-10'd31;

//==========================================================
///同步信号产生
//==========================================================
reg hsync_r,vsync_r;

always @ (posedge clk or negedge rst_n)
begin
if(!rst_n) hsync_r <= 1'b1;
else if(x_cnt == 11'd0) hsync_r <= 1'b0; //产生hsync信号
else if(x_cnt == 11'd120) hsync_r <= 1'b1;
end

always @ (posedge clk or negedge rst_n)
begin
if(!rst_n) vsync_r <= 1'b1;
else if(y_cnt == 10'd0) vsync_r <= 1'b0; //产生vsync信号
else if(y_cnt == 10'd6) vsync_r <= 1'b1;
end

assign hsync = hsync_r;
assign vsync = vsync_r;

//==========================================================
//显示一个矩形框
//==========================================================
wire a_dis,b_dis,c_dis,d_dis; //矩形框显示区域定位

assign a_dis = ( (xpos>=200) && (xpos<=220) )
&& ( (ypos>=140) && (ypos<=460) );

assign b_dis = ( (xpos>=580) && (xpos<=600) )
&& ( (ypos>=140) && (ypos<=460) );

assign c_dis = ( (xpos>=220) && (xpos<=580) )
&& ( (ypos>140) && (ypos<=160) );

assign d_dis = ( (xpos>=220) && (xpos<=580) )
&& ( (ypos>=440) && (ypos<=460) );

//显示一个小矩形
wire e_rdy; //矩形的显示有效矩形区域

assign e_rdy = ( (xpos>=385) && (xpos<=415) )
&& ( (ypos>=285) && (ypos<=315) );

//==========================================================
//r,g,b控制液晶屏颜色显示，背景显示蓝色，矩形框显示红蓝色
//==========================================================
assign vga_r = valid ? e_rdy : 1'b0;
assign vga_g = valid ? (a_dis | b_dis | c_dis | d_dis) : 1'b0;
assign vga_b = valid ? ~(a_dis | b_dis | c_dis | d_dis) : 1'b0;

endmodule

UCF 文件：

NET "clk" LOC = Y9;
NET "out" LOC = T22;

NET "clk" IOSTANDARD = LVCMOS33;
NET "out" IOSTANDARD = LVCMOS33;
NET "clk" PULLUP;
NET "out" PULLUP;

# PlanAhead Generated physical constraints

NET "sys_clk" LOC = Y9;
NET "vga_r" LOC = V20;
NET "vga_g" LOC = B22;
NET "vga_b" LOC = Y20;
NET "hsync" LOC = AA19;
NET "vsync" LOC = Y19;

# PlanAhead Generated IO constraints

NET "sys_clk" IOSTANDARD = LVCMOS33;
NET "vga_b" IOSTANDARD = LVCMOS33;
NET "vga_g" IOSTANDARD = LVCMOS33;
NET "vga_r" IOSTANDARD = LVCMOS33;
NET "vsync" IOSTANDARD = LVCMOS33;
NET "hsync" IOSTANDARD = LVCMOS33;
NET "hsync" PULLUP;

NET "sys_clk" PULLUP;
NET "vga_b" PULLUP;
NET "vga_g" PULLUP;
NET "vga_r" PULLUP;
NET "vsync" PULLUP;

我是用notepad++ 编辑的，tab 在这里搞成了空格，notepad是可以设置tab为空格模式。用tab习惯了，不喜欢吧tab 设置成空格模式，一直保持直接跳跃的模式，大家见谅。