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FPGA 下面dac调试

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最近自己做了一套板子,弄了个DAC,一时不知道怎么去调试的好,今天闲来没事,调试了一下,代码一起哈成,无修改。代码也比较简陋,做了一个DAC 的典雅线性变化。这里就直接观察LED 灯的变化,跟PWM 实现的 LED 亮度变化差不多吧!

具体电路见这里:

时序:

这里的时序我分为 CS 拉低,WR拉低和赋值。WR拉高,CS拉高 4个阶段,

代码:

module dac
(
sys_clk,reset_b,
wr,cs,data
);
input sys_clk,reset_b;
output [7:0] data;
output wr,cs;

reg wr,cs;
reg adc_clk;
reg [7:0] data,data_buf;
reg [2:0] next;

parameter state1 =3'd0;
parameter state2 =3'd1;
parameter state3 =3'd2;
parameter state4 =3'd3;
reg[15:0] count;
always @ (posedge sys_clk)
begin
if(!reset_b)
begin
count<=16'd0;
adc_clk<=1'b1;
end
else
if(count==16'd100)
begin
count<=16'd0;
adc_clk<=~adc_clk;
end
else count<=count+1'b1;
end
//=========data buf add=================
reg[20:0] count_adc;
always @ (posedge sys_clk)
begin
if(!reset_b)
begin
count_adc<=21'd0;
data_buf<=8'b0;
end
else
if(count_adc==21'd50000000)
begin
count_adc<=21'd0;
data_buf<=data_buf+1'b1;
end
else count_adc<=count_adc+1'b1;
end


always @ (posedge adc_clk)
begin
if(!reset_b)
begin
next<=state1;
cs<=1'b1;
wr<=1'b1;
end
else
case (next)
state1 :
begin
cs<=1'b0;
next<=state2;
end
state2 :
begin
wr<=1'b0;
data<=data_buf;
next<=state3;
end
state3 :
begin
wr<=1'b1;
next<=state4;
end
state4 :
begin
cs<=1'b1;
next<=state1;
end
endcase

end


endmodule

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