参照艾米电子的程序进行改写的

//date : 2014,5,4 module for_beep ( clock , reset , out_beep ); input clock ,reset ; output reg out_beep ; reg [2:0] state ; reg [3:0] clk1 ; reg [12:0] cnt0 ; reg [24:0] delay_cnt1; parameter du = 4775 , re = 4255 , mi = 3790 , fa = 3580 , so = 3185 , la = 2840 , xi = 2530 , do1 = 2385 ; always @ (posedge clock or negedge reset ) begin if (!reset ) begin clk1 <= 4'd0 ; state <= 3'd0 ; cnt0 <= 13'd0 ; delay_cnt1 <= 24'd0 ; out_beep <= 1'd0 ; end else if(clk1 == 4'd8) begin case (state) 3'd0 : begin delay_cnt1 <= delay_cnt1 + 24'd1; if(delay_cnt1 == 25'h1ff_ffff) state <= 3'd1 ; if(cnt0 != du) cnt0 <= cnt0 + 13'd1 ; else begin cnt0 <= 13'd0 ; out_beep <= ~out_beep ; end end 3'd1 : begin delay_cnt1 <= delay_cnt1 + 24'd1; if(delay_cnt1 == 25'h1ff_ffff) state <= 3'd2 ; if(cnt0 != re) cnt0 <= cnt0 + 13'd1 ; else begin cnt0 <= 13'd0 ; out_beep <= ~out_beep ; end end 3'd2 : begin delay_cnt1 <= delay_cnt1 + 24'd1; if(delay_cnt1 == 25'h1ff_ffff) state <= 3'd3 ; if(cnt0 != mi) cnt0 <= cnt0 + 13'd1 ; else begin cnt0 <= 13'd0 ; out_beep <= ~out_beep ; end end 3'd3 : begin delay_cnt1 <= delay_cnt1 + 24'd1; if(delay_cnt1 == 25'h1ff_ffff) state <= 3'd4 ; if(cnt0 != fa) cnt0 <= cnt0 + 13'd1 ; else begin cnt0 <= 13'd0 ; out_beep <= ~out_beep ; end end 3'd4 : begin delay_cnt1 <= delay_cnt1 + 24'd1; if(delay_cnt1 == 25'h1ff_ffff) state <= 3'd5 ; if(cnt0 != so) cnt0 <= cnt0 + 13'd1 ; else begin cnt0 <= 13'd0 ; out_beep <= ~out_beep ; end end 3'd5 : begin delay_cnt1 <= delay_cnt1 + 24'd1; if(delay_cnt1 == 25'h1ff_ffff) state <= 3'd6 ; if(cnt0 != la) cnt0 <= cnt0 + 13'd1 ; else begin cnt0 <= 13'd0 ; out_beep <= ~out_beep ; end end 3'd6 : begin delay_cnt1 <= delay_cnt1 + 24'd1; if(delay_cnt1 == 25'h1ff_ffff) state <= 3'd7 ; if(cnt0 != xi) cnt0 <= cnt0 + 13'd1 ; else begin cnt0 <= 13'd0 ; out_beep <= ~out_beep ; end end 3'd7 : begin delay_cnt1 <= delay_cnt1 + 24'd1; if(delay_cnt1 == 25'h1ff_ffff) state <= 3'd0 ; if(cnt0 != do1) cnt0 <= cnt0 + 13'd1 ; else begin cnt0 <= 13'd0 ; out_beep <= ~out_beep ; end end endcase end else if(clk1 < 4'd9 ) clk1 <= clk1 + 4'd1 ; else clk1 <= 4'd0 ; end endmodule