// date : 2013,3,18

//designer : pengxiaoen

// function:the T of the output_clk is three times of clk

module clock_3 (

　　　　　　　　　　clk,reset,

　　　　　　　　　　clk_temp,output_clk

) ;

input clk,reset;

output clk_temp,output_clk ;

reg output_clk;

reg [31:0] temp;

//-----------------------------------------------

always @ (posedge clk or negedge reset)

if (!reset)

　　 temp <= 32'd0;

else if (temp[25] == 1)

　　　　temp <= 32'd0;

　　else temp = temp+1;

reg clock_temp;

//----------------------------------------------- 随便进行了一个分频，因为我的基准时钟要绑定在一个led上，当然就不可以把50M当成基准了

always @ (posedge clk or negedge reset)

if (!reset) clock_temp <= 1'b0;

else if (temp[25]) clock_temp <= ~clock_temp;

reg [1:0] a,b; //--------------------------------------------------

always @ (posedge clock_temp or negedge reset )

if (!reset) a <= 2'd0;

else if (a==2'd2) a<=2'd0;

　　else a = a+1;

always @ (negedge clock_temp or negedge reset)

if (!reset) b <= 2'd0;

else if (b == 2'd2) b <= 2'd0;

　　 else b <= b+1;

always @ (a or b)

if ((a== 2'd0) && (b == 2'd2)) output_clk <= 1'b1;

else if ((a ==2'd1) &&(b == 2'd1)) output_clk <= 1'b0;

　　 else;

assign clk_temp = clock_temp;

endmodule