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dsp--28335的cmd文件学习(二)

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今天调试28335发现出现了错误error: can't allocate .ebss, size 00000400 (page 1) in RAMM1 (avail: 00000380),网上找答案都是改Stack Size,改成小于1024,我一看我早就改了,于是静下心来找答案,发现ebss是未初始化的变量存放的空间,于是在程序中将一些以前调试而没有删除的变量删除了,编译就果断ok了,问题是解决了,但是觉得自己关于cmd文件的学习太过草率了,于是,学习一些28335的cmd文件。ps:在去年的笔记中也发现中发现了error: can't allocate .text太大的原因,但是的解决办法是将一些多余的c文件删除就行了,但是还不知道为什么,现在可以解释了。

转载请注明;来自xzyfeixiang的博客:http://blog.csdn.net/xzyiverson

首先,我们必须要知道一些基本的概念,然后再分析,这里引用书本的一些话。




28335的cmd文件有两个,一个是关于寄存器的,一个是关于程序的。

关于寄存器的cmd文件,包括两部分,一部分是section,这部分是定义的寄存器文件,一部分是map,就是为那些寄存器文件分配地址:

[html] view plain copy 在CODE上查看代码片 派生到我的代码片
  1. MEMORY
  2. {
  3. PAGE 0: /* Program Memory */
  4. PAGE 1: /* Data Memory */
  5. DEV_EMU :origin=0x000880,length=0x000180/* device emulation registers */
  6. FLASH_REGS :origin=0x000A80,length=0x000060/* FLASH registers */
  7. CSM :origin=0x000AE0,length=0x000010/* code security module registers */
  8. ADC_MIRROR :origin=0x000B00,length=0x000010/* ADC Results register mirror */
  9. XINTF :origin=0x000B20,length=0x000020/* external interface registers */
  10. CPU_TIMER0 :origin=0x000C00,length=0x000008/* CPU Timer0 registers */
  11. CPU_TIMER1 :origin=0x000C08,length=0x000008/* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
  12. CPU_TIMER2 :origin=0x000C10,length=0x000008/* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
  13. PIE_CTRL :origin=0x000CE0,length=0x000020/* PIE control registers */
  14. PIE_VECT :origin=0x000D00,length=0x000100/* PIE Vector Table */
  15. DMA :origin=0x001000,length=0x000200/* DMA Rev 0 registers */
  16. MCBSPA :origin=0x005000,length=0x000040/* McBSP-A registers */
  17. MCBSPB :origin=0x005040,length=0x000040/* McBSP-B registers */
  18. ECANA :origin=0x006000,length=0x000040/* eCAN-A control and status registers */
  19. ECANA_LAM :origin=0x006040,length=0x000040/* eCAN-A local acceptance masks */
  20. ECANA_MOTS :origin=0x006080,length=0x000040/* eCAN-A message object time stamps */
  21. ECANA_MOTO :origin=0x0060C0,length=0x000040/* eCAN-A object time-out registers */
  22. ECANA_MBOX :origin=0x006100,length=0x000100/* eCAN-A mailboxes */
  23. ECANB :origin=0x006200,length=0x000040/* eCAN-B control and status registers */
  24. ECANB_LAM :origin=0x006240,length=0x000040/* eCAN-B local acceptance masks */
  25. ECANB_MOTS :origin=0x006280,length=0x000040/* eCAN-B message object time stamps */
  26. ECANB_MOTO :origin=0x0062C0,length=0x000040/* eCAN-B object time-out registers */
  27. ECANB_MBOX :origin=0x006300,length=0x000100/* eCAN-B mailboxes */
  28. EPWM1 :origin=0x006800,length=0x000022/* Enhanced PWM 1 registers */
  29. EPWM2 :origin=0x006840,length=0x000022/* Enhanced PWM 2 registers */
  30. EPWM3 :origin=0x006880,length=0x000022/* Enhanced PWM 3 registers */
  31. EPWM4 :origin=0x0068C0,length=0x000022/* Enhanced PWM 4 registers */
  32. EPWM5 :origin=0x006900,length=0x000022/* Enhanced PWM 5 registers */
  33. EPWM6 :origin=0x006940,length=0x000022/* Enhanced PWM 6 registers */
  34. ECAP1 :origin=0x006A00,length=0x000020/* Enhanced Capture 1 registers */
  35. ECAP2 :origin=0x006A20,length=0x000020/* Enhanced Capture 2 registers */
  36. ECAP3 :origin=0x006A40,length=0x000020/* Enhanced Capture 3 registers */
  37. ECAP4 :origin=0x006A60,length=0x000020/* Enhanced Capture 4 registers */
  38. ECAP5 :origin=0x006A80,length=0x000020/* Enhanced Capture 5 registers */
  39. ECAP6 :origin=0x006AA0,length=0x000020/* Enhanced Capture 6 registers */
  40. EQEP1 :origin=0x006B00,length=0x000040/* Enhanced QEP 1 registers */
  41. EQEP2 :origin=0x006B40,length=0x000040/* Enhanced QEP 2 registers */
  42. GPIOCTRL :origin=0x006F80,length=0x000040/* GPIO control registers */
  43. GPIODAT :origin=0x006FC0,length=0x000020/* GPIO data registers */
  44. GPIOINT :origin=0x006FE0,length=0x000020/* GPIO interrupt/LPM registers */
  45. SYSTEM :origin=0x007010,length=0x000020/* System control registers */
  46. SPIA :origin=0x007040,length=0x000010/* SPI-A registers */
  47. SCIA :origin=0x007050,length=0x000010/* SCI-A registers */
  48. XINTRUPT :origin=0x007070,length=0x000010/* external interrupt registers */
  49. ADC :origin=0x007100,length=0x000020/* ADC registers */
  50. SCIB :origin=0x007750,length=0x000010/* SCI-B registers */
  51. SCIC :origin=0x007770,length=0x000010/* SCI-C registers */
  52. I2CA :origin=0x007900,length=0x000040/* I2C-A registers */
  53. CSM_PWL :origin=0x33FFF8,length=0x000008/* Part of FLASHA. CSM password locations. */
  54. }
  55. SECTIONS
  56. {
  57. PieVectTableFile :>PIE_VECT,PAGE=1
  58. /*** Peripheral Frame 0 Register Structures ***/
  59. DevEmuRegsFile :>DEV_EMU,PAGE=1
  60. FlashRegsFile :>FLASH_REGS,PAGE=1
  61. CsmRegsFile :>CSM,PAGE=1
  62. AdcMirrorFile :>ADC_MIRROR,PAGE=1
  63. XintfRegsFile :>XINTF,PAGE=1
  64. CpuTimer0RegsFile :>CPU_TIMER0,PAGE=1
  65. CpuTimer1RegsFile :>CPU_TIMER1,PAGE=1
  66. CpuTimer2RegsFile :>CPU_TIMER2,PAGE=1
  67. PieCtrlRegsFile :>PIE_CTRL,PAGE=1
  68. DmaRegsFile :>DMA,PAGE=1
  69. /*** Peripheral Frame 3 Register Structures ***/
  70. McbspaRegsFile :>MCBSPA,PAGE=1
  71. McbspbRegsFile :>MCBSPB,PAGE=1
  72. /*** Peripheral Frame 1 Register Structures ***/
  73. ECanaRegsFile :>ECANA,PAGE=1
  74. ECanaLAMRegsFile :>ECANA_LAMPAGE=1
  75. ECanaMboxesFile :>ECANA_MBOXPAGE=1
  76. ECanaMOTSRegsFile :>ECANA_MOTSPAGE=1
  77. ECanaMOTORegsFile :>ECANA_MOTOPAGE=1
  78. ECanbRegsFile :>ECANB,PAGE=1
  79. ECanbLAMRegsFile :>ECANB_LAMPAGE=1
  80. ECanbMboxesFile :>ECANB_MBOXPAGE=1
  81. ECanbMOTSRegsFile :>ECANB_MOTSPAGE=1
  82. ECanbMOTORegsFile :>ECANB_MOTOPAGE=1
  83. EPwm1RegsFile :>EPWM1PAGE=1
  84. EPwm2RegsFile :>EPWM2PAGE=1
  85. EPwm3RegsFile :>EPWM3PAGE=1
  86. EPwm4RegsFile :>EPWM4PAGE=1
  87. EPwm5RegsFile :>EPWM5PAGE=1
  88. EPwm6RegsFile :>EPWM6PAGE=1
  89. ECap1RegsFile :>ECAP1PAGE=1
  90. ECap2RegsFile :>ECAP2PAGE=1
  91. ECap3RegsFile :>ECAP3PAGE=1
  92. ECap4RegsFile :>ECAP4PAGE=1
  93. ECap5RegsFile :>ECAP5PAGE=1
  94. ECap6RegsFile :>ECAP6PAGE=1
  95. EQep1RegsFile :>EQEP1PAGE=1
  96. EQep2RegsFile :>EQEP2PAGE=1
  97. GpioCtrlRegsFile :>GPIOCTRLPAGE=1
  98. GpioDataRegsFile :>GPIODATPAGE=1
  99. GpioIntRegsFile :>GPIOINTPAGE=1
  100. /*** Peripheral Frame 2 Register Structures ***/
  101. SysCtrlRegsFile :>SYSTEM,PAGE=1
  102. SpiaRegsFile :>SPIA,PAGE=1
  103. SciaRegsFile :>SCIA,PAGE=1
  104. XIntruptRegsFile :>XINTRUPT,PAGE=1
  105. AdcRegsFile :>ADC,PAGE=1
  106. ScibRegsFile :>SCIB,PAGE=1
  107. ScicRegsFile :>SCIC,PAGE=1
  108. I2caRegsFile :>I2CA,PAGE=1
  109. /*** Code Security Module Register Structures ***/
  110. CsmPwlFile :>CSM_PWL,PAGE=1

关于寄存器的cmd文件没有什么很难理解的地方,关键是程序的cmd文件,要好好学习一下。

[html] view plain copy 在CODE上查看代码片 派生到我的代码片
  1. MEMORY
  2. {
  3. PAGE 0 :
  4. /* BEGIN is used for the "boot to SARAM" bootloader mode */
  5. /* BOOT_RSVD is used by the boot ROM for stack. */
  6. /* This section is only reserved to keep the BOOT ROM from */
  7. /* corrupting this area during the debug process */
  8. BEGIN :origin=0x000000,length=0x000002/* Boot to M0 will go here */
  9. BOOT_RSVD :origin=0x000002,length=0x00004E/* Part of M0, BOOT rom will use this for stack */
  10. RAMM0 :origin=0x000050,length=0x0003B0
  11. RAML0 :origin=0x008000,length=0x001000
  12. RAML1 :origin=0x009000,length=0x001000
  13. RAML2 :origin=0x00A000,length=0x001000
  14. RAML3 :origin=0x00B000,length=0x001000
  15. ZONE6A :origin=0x100000,length=0x00FC00/* XINTF zone 6 - program space */
  16. CSM_RSVD :origin=0x33FF80,length=0x000076/* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
  17. CSM_PWL :origin=0x33FFF8,length=0x000008/* Part of FLASHA. CSM password locations in FLASHA */
  18. ADC_CAL :origin=0x380080,length=0x000009
  19. RESET :origin=0x3FFFC0,length=0x000002
  20. IQTABLES :origin=0x3FE000,length=0x000b50
  21. IQTABLES2 :origin=0x3FEB50,length=0x00008c
  22. FPUTABLES :origin=0x3FEBDC,length=0x0006A0
  23. BOOTROM :origin=0x3FF27C,length=0x000D44
  24. PAGE 1 :
  25. RAMM1 :origin=0x000400,length=0x000400/* on-chip RAM block M1 */
  26. RAML4 :origin=0x00C000,length=0x001000
  27. RAML5 :origin=0x00D000,length=0x001000
  28. RAML6 :origin=0x00E000,length=0x001000
  29. RAML7 :origin=0x00F000,length=0x001000
  30. ZONE6B :origin=0x10FC00,length=0x000400/* XINTF zone 6 - data space */
  31. }
  32. SECTIONS
  33. {
  34. /* Setup for "boot to SARAM" mode:
  35. The codestart section (found in DSP28_CodeStartBranch.asm)
  36. re-directs execution to the start of user code. */
  37. codestart :>BEGIN,PAGE=0
  38. ramfuncs :>RAML0,PAGE=0
  39. .text :>RAML1,PAGE=0
  40. .cinit :>RAML0,PAGE=0
  41. .pinit :>RAML0,PAGE=0
  42. .switch :>RAML0,PAGE=0
  43. .stack :>RAMM1,PAGE=1
  44. .ebss :>RAML4,PAGE=1
  45. .econst :>RAML5,PAGE=1
  46. .esysmem :>RAMM1,PAGE=1
  47. IQmath :>RAML1,PAGE=0
  48. IQmathTables :>IQTABLES,PAGE=0,TYPE=NOLOAD
  49. IQmathTables2 :>IQTABLES2,PAGE=0,TYPE=NOLOAD
  50. FPUmathTables :>FPUTABLES,PAGE=0,TYPE=NOLOAD
  51. DMARAML4 :>RAML4,PAGE=1
  52. DMARAML5 :>RAML5,PAGE=1
  53. DMARAML6 :>RAML6,PAGE=1
  54. DMARAML7 :>RAML7,PAGE=1
  55. ZONE6DATA :>ZONE6B,PAGE=1
  56. .reset :>RESET,PAGE=0,TYPE=DSECT/* not used */
  57. csm_rsvd :>CSM_RSVDPAGE=0,TYPE=DSECT/* not used for SARAM examples */
  58. csmpasswds :>CSM_PWLPAGE=0,TYPE=DSECT/* not used for SARAM examples */
  59. /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
  60. .adc_cal :load=ADC_CAL,PAGE=0,TYPE=NOLOAD
  61. }

也是分为两个部分,下面是段,上面是为那些段分配的地址,当然有些段在程序中比较大,但是给他分配的地址又不够,这个时候就报错了,这个时候需要修改程序或者修改cmd文件了,这样,大致的思路就清晰了。PAGE 0代表程序空间, PAGE 1代表数据空间,我们可以将一个大的空间分成两部分,然后将一些段放在这两部分空间里,但这两空间的总和不能超过原有的空间,上述是运行在ram的cmd文件,下面这个cmd文件我报错的cmd文件,对比一下就可以知道原因了。

[html] view plain copy 在CODE上查看代码片 派生到我的代码片
  1. MEMORY
  2. {
  3. PAGE 0: /* Program Memory */
  4. /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
  5. ZONE0 :origin=0x004000,length=0x001000/* XINTF zone 0 */
  6. RAM_L0L1L2L3:origin=0x008000,length=0x004000/* on-chip RAM */
  7. OTP :origin=0x380400,length=0x000400/* on-chip OTP */
  8. ZONE6 :origin=0x100000,length=0x100000/* XINTF zone 6 */
  9. ZONE7A :origin=0x200000,length=0x00FC00/* XINTF zone 7 - program space */
  10. FLASHH :origin=0x300000,length=0x008000/* on-chip FLASH */
  11. FLASHG :origin=0x308000,length=0x008000/* on-chip FLASH */
  12. FLASHF :origin=0x310000,length=0x008000/* on-chip FLASH */
  13. FLASHE :origin=0x318000,length=0x008000/* on-chip FLASH */
  14. FLASHD :origin=0x320000,length=0x008000/* on-chip FLASH */
  15. FLASHC :origin=0x328000,length=0x008000/* on-chip FLASH */
  16. FLASHA :origin=0x338000,length=0x007F80/* on-chip FLASH */
  17. CSM_RSVD :origin=0x33FF80,length=0x000076/* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
  18. BEGIN_FLASH :origin=0x33FFF6,length=0x000002/* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
  19. CSM_PWL :origin=0x33FFF8,length=0x000008/* Part of FLASHA. CSM password locations in FLASHA */
  20. ADC_CAL :origin=0x380080,length=0x000009/* Part of TI OTP */
  21. IQTABLES :origin=0x3FE000,length=0x000b50/* IQ Math Tables in Boot ROM */
  22. IQTABLES2 :origin=0x3FEB50,length=0x00008c/* IQ Math Tables in Boot ROM */
  23. FPUTABLES :origin=0x3FEBDC,length=0x0006A0/* FPU Tables in Boot ROM */
  24. ROM :origin=0x3FF27C,length=0x000D44/* Boot ROM */
  25. RESET :origin=0x3FFFC0,length=0x000002/* part of boot ROM */
  26. VECTORS :origin=0x3FFFC2,length=0x00003E/* part of boot ROM */
  27. PAGE 1 : /* Data Memory */
  28. /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
  29. /* Registers remain on PAGE1 */
  30. RAMM0 :origin=0x000000,length=0x000400/* on-chip RAM block M0 */
  31. BOOT_RSVD :origin=0x000400,length=0x000080/* Part of M1, BOOT rom will use this for stack */
  32. RAMM1 :origin=0x000480,length=0x000380/* on-chip RAM block M1 */
  33. RAML4 :origin=0x00C000,length=0x001000/* on-chip RAM block L4 */
  34. RAML5 :origin=0x00D000,length=0x001000/* on-chip RAM block L5 */
  35. RAML6 :origin=0x00E000,length=0x001000/* on-chip RAM block L6 */
  36. RAML7 :origin=0x00F000,length=0x001000/* on-chip RAM block L7 */
  37. ZONE7B :origin=0x20FC00,length=0x000400/* XINTF zone 7 - data space */
  38. }
  39. /**************************************************************/
  40. /* Link all user defined sections */
  41. /**************************************************************/
  42. SECTIONS
  43. {
  44. /*** Code Security Password Locations ***/
  45. csmpasswds :>CSM_PWLPAGE=0
  46. csm_rsvd :>CSM_RSVDPAGE=0
  47. /*** User Defined Sections ***/
  48. codestart :>BEGIN_FLASH,PAGE=0/* Used by file CodeStartBranch.asm */
  49. wddisable :>FLASHA,PAGE=0
  50. copysections :>FLASHA,PAGE=0
  51. /* Allocate IQ math areas: */
  52. IQmath :>FLASHCPAGE=0/* Math Code */
  53. IQmathTables :>IQTABLES,PAGE=0,TYPE=NOLOAD
  54. IQmathTables2 :>IQTABLES2,PAGE=0,TYPE=NOLOAD
  55. FPUmathTables :>FPUTABLES,PAGE=0,TYPE=NOLOAD
  56. /* Allocate DMA-accessible RAM sections: */
  57. DMARAML4 :>RAML4,PAGE=1
  58. DMARAML5 :>RAML5,PAGE=1
  59. DMARAML6 :>RAML6,PAGE=1
  60. DMARAML7 :>RAML7,PAGE=1
  61. /* Allocate 0x400 of XINTF Zone 7 to storing data */
  62. ZONE7DATA :>ZONE7B,PAGE=1
  63. /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
  64. .adc_cal :load=ADC_CAL,PAGE=0,TYPE=NOLOAD
  65. /* .reset is a standard section used by the compiler. It contains the */
  66. /* the address of the start of _c_int00 for C Code. /*
  67. /* When using the boot ROM this section and the CPU vector */
  68. /* table is not needed. Thus the default type is set here to */
  69. /* DSECT */
  70. .reset :>RESET,PAGE=0,TYPE=DSECT
  71. vectors :>VECTORSPAGE=0,TYPE=DSECT
  72. /*** Uninitialized Sections ***/
  73. .stack :>RAMM0PAGE=1
  74. .ebss :>RAMM1PAGE=1
  75. .esysmem :>RAMM1PAGE=1
  76. /*** Initialized Sections ***/
  77. .cinit :LOAD=FLASHA,PAGE=0/* can be ROM */
  78. RUN=RAM_L0L1L2L3,PAGE=0/* must be CSM secured RAM */
  79. LOAD_START(_cinit_loadstart),
  80. RUN_START(_cinit_runstart),
  81. SIZE(_cinit_size)
  82. .const :LOAD=FLASHA,PAGE=0/* can be ROM */
  83. RUN=RAM_L0L1L2L3,PAGE=0/* must be CSM secured RAM */
  84. LOAD_START(_const_loadstart),
  85. RUN_START(_const_runstart),
  86. SIZE(_const_size)
  87. .econst :LOAD=FLASHA,PAGE=0/* can be ROM */
  88. RUN=RAM_L0L1L2L3,PAGE=0/* must be CSM secured RAM */
  89. LOAD_START(_econst_loadstart),
  90. RUN_START(_econst_runstart),
  91. SIZE(_econst_size)
  92. .pinit :LOAD=FLASHA,PAGE=0/* can be ROM */
  93. RUN=RAM_L0L1L2L3,PAGE=0/* must be CSM secured RAM */
  94. LOAD_START(_pinit_loadstart),
  95. RUN_START(_pinit_runstart),
  96. SIZE(_pinit_size)
  97. .switch :LOAD=FLASHA,PAGE=0/* can be ROM */
  98. RUN=RAM_L0L1L2L3,PAGE=0/* must be CSM secured RAM */
  99. LOAD_START(_switch_loadstart),
  100. RUN_START(_switch_runstart),
  101. SIZE(_switch_size)
  102. .text :LOAD=FLASHA,PAGE=0/* can be ROM */
  103. RUN=RAM_L0L1L2L3,PAGE=0/* must be CSM secured RAM */
  104. LOAD_START(_text_loadstart),
  105. RUN_START(_text_runstart),
  106. SIZE(_text_size)
  107. }

看下M1分成了两个部分,ebss的部分当然就没有0x400了,这也是为什么会报错的原因了,这是学习cmd文件最基本的东西,要真正学好还有很长的一段距离,只能慢慢来了。


上面这张图为编译工程文件时的链接过程,可以解决我们一部分的疑惑。也解释了我第一段中text过大的原因,在工程中有些文件你虽然没有调用,但是他是占text的空间的,这也是我最初删除了一些不用的c文件就编译成功的原因。

最后:排爆机器人基于dsp+fpga中有些特色还没写出来,包括串口状态机(这部分比较好,继承师兄的),还有就是dsp读写fpga这部分吧(基于xintf的),然后还用到了pwm模块,哦,还有一个就是烧写到flash里面,拷贝到ram里面运行,不过这东西是借鉴的别人的,慢慢记录下来吧。


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