在许多应用中只将异步时钟信号同步化还是不够的，当系统中有两个或两个以上非同源时钟的时候，数据的建立和保持时间很难得到保证。这时候，可以将所有非同源时钟同步化。在电路中引入一个高频时钟来实现信号的同步化。如下图所示：

看到这个图，我当时理解了很长时间。做个实验验证下。

写出代码如下：

module Multi_clk(rst_n,clk_4M,clk_5M,clk_20M,Data_in,Data_out,EN_4M,EN_5M); input clk_4M; input clk_5M; input clk_20M; input Data_in; input rst_n; output Data_out; output EN_4M; output EN_5M; reg Data_out_r; reg clk_4M_r1; reg clk_4M_r2; reg clk_5M_r1; reg clk_5M_r2; always@(posedge clk_20M or negedge rst_n) begin if(!rst_n) begin clk_4M_r1<=1'b0; clk_4M_r2<=1'b0; clk_5M_r1<=1'b0; clk_5M_r2<=1'b0; end else begin clk_4M_r1<=clk_4M; clk_4M_r2<=clk_4M_r1; clk_5M_r1<=clk_5M; clk_5M_r2<=clk_5M_r1; end end wire EN_4M; wire EN_5M; assign EN_4M=clk_4M_r1 & ~clk_4M_r2; assign EN_5M=clk_5M_r1 & ~clk_5M_r2; always@(posedge clk_20M or negedge rst_n) begin if(!rst_n) Data_out_r<=1'b0; else if((EN_4M==1) || (EN_5M==1) ) Data_out_r<=Data_in; else Data_out_r<=Data_out_r; end assign Data_out=Data_out_r; endmodule

Testbench如下所示：

`timescale 1 ps/ 1 ps module Multi_clk(); reg Data_in; reg clk_4M; reg clk_5M; wire EN_4M; wire EN_5M; reg clk_20M; reg rst_n; wire Data_out; Multi_clk i1 ( .Data_in(Data_in), .Data_out(Data_out), .clk_4M(clk_4M), .clk_5M(clk_5M), .clk_20M(clk_20M), .rst_n(rst_n), .EN_4M(EN_4M), .EN_5M(EN_5M) ); initial begin rst_n=1'b0; #100 rst_n=1'b1; end parameter PERIOD_20M=50; parameter PERIOD_4M=250; parameter PERIOD_5M=200; initial begin clk_20M=0; forever clk_20M=#(PERIOD_20M/2)~clk_20M; end initial begin clk_4M=0; forever clk_4M=#(PERIOD_4M/2)~clk_4M; end initial begin clk_5M=0; forever clk_5M=#(PERIOD_5M/2)~clk_5M; end initial begin Data_in=1'b0; #1000; @(posedge clk_20M) Data_in=1'b1; #1000; @(posedge clk_20M) Data_in=1'b0; #1000; @(posedge clk_20M) Data_in=1'b1; #1000; @(posedge clk_20M) Data_in=1'b0; #1000; @(posedge clk_20M) Data_in=1'b1; #1000; @(posedge clk_20M) Data_in=1'b0; #1000; end endmodule

分析下波形如下所示：

搞了半天，原来上面的电路就是两个边沿检测电路，然后利用高频时钟来采样低频时钟。基础不行，一时真没反应过来。