module Image_Converter_Baseline #(parameter pixel_size=8,N_col=8, M_row=6)( output [1:N_col*M_row] HTPV_bits, input [1:pixel_size*N_col*M_row] pixel_bits ); wire HTPV [1:N_col][1:M_row]; wire [pixel_size-1:0]Err[0:N_col+1][0:M_row]; genvar n,m; generate for(n=0;n<=N_col+1;n=n+1)begin:top_border assign Err[n][0]=1'b0;end for(m=1;m<=M_row;m=m+1) begin:left_border assign Err[0][m]=1'b0;end for(m=1;m<=M_row;m=m+1) begin:right_border assign Err[N_col+1][m]=1'b0;end for(m=1;m<=M_row;m=m+1) begin:row_loop for(n=1;n<=N_col;n=n+1) begin:column_loop PPDU M(Err[n][m],HTPV[n][m],Err[n-1][m],Err[n-1][m-1],Err[n][m-1], Err[n+1][m-1], pixel_bits[(m-1)*N_col*pixel_size+(n-1)*pixel_size+1:(m-1)* N_col*pixel_size+n*pixel_size]); end end endgenerate generate for(m=1;m<=M_row;m=m+1)begin:HTPV_row_loop for(n=1;n>4; assign CPV=PV+E_av; assign CPV_round=(CPV
       选了好几个器件才能综合，主要是输入引脚也太多了吧，最恐怖的是RTL视图。。。。，看的眼花缭乱。Verilog HDL在循环语句中综合出来的结果总是让人汗颜。。由此可见，以后的程序还是尽量少用还是不用for循环吧》》》》》》》》