W5300是一款全硬件TCP/IP协议嵌入式以太网控制芯片,用于要求高速的嵌入式系统。

内部TX/RX存储器

W5300内部集成128KB存储器用于通信。该存储器根据TMSR和RMSR的寄存器设置分成TX和RX存储器，并在每一个Socket端口又重新划分为对应端口的TX和RX存储器。

用户不能从主机直接访问内部TX/RX存储器，但是可以通过每个Socket端口的FIFO寄存器间接访问。并且通过使用Sn_TX_FIFOR和Sn_RX_FIFOR，可以间接访问TX和RX存储器。

在W5300正常工作时，TX存储器只允许通过Sn_TX_FIFOR进行主机写操作，RX存储器只允许通过Sn_RX_FIFOR进行主机读操作。为了检查主机是否将数据正确地写入TX存储器，主机是否正确地从RX存储器读出数据，W5300需要工作在存储器测试模式。

发送（TX）存储器具有内部访问指针。无论何时主机写Sn_TX_FIFOR，内部访问指针都会自Sn_TX_FIFOR存入SOCKET n的TX缓存后，以2byte的偏移量从基址增加到TX缓存的终点。

访问指针自基址向TX内存的终点增加，为了防止主机持续的写入Sn_TX_FIFOR，当Sn_TX_FIFOR写满指定大小寄存器，访问指针会从终点返回基址起始位置。一般来说，访问指针的自动增加和回滚功能防止了Sn_TX_FIFOR的Host-Write。然而，如果MR寄存器的MT位设置为‘1’，此功能甚至能够避免Sn_TX_FIFOR的Host-Read. 因此，此功能可以验证发送（TX）内存的Host-Write操作。

Sn_RX_FIFOR & RX 存储器

接收（RX）存储器也具有内部访问指针。无论何时主机读Sn_RX_FIFOR，内部访问指针都会自Sn_RX_FIFOR存入SOCKET n的RX缓存后，以2byte的偏移量从基址增加到RX缓存的终点。

当主机持续地从访问指针读取Sn_RX_FIFOR到终点时，访问指针又回到基点。当Sn_RX_FIFOR读取的数据与分配的存储器大小相同时，访问存储器就会回到起点。通常，访问指针增加和回滚功能只是避免Sn_RX_FIFOR的Host-Read。可是，如果MR的‘MT’位被设置为‘1’，那么这个功能甚至能够避免Sn_RX_FIFOR的Host-Write。使用该功能可以验证发送（RX）存储器的Host-Read操作。

如何测试 SOCKET 存储器

测试步骤如下：

• W5300初始化
• SOCKET存储器分配
• 设置MR的MT位
• 打开SOCKET n
• SOCKET n存储器测试
• 关闭SOCKET n
• 复位MR的MT位

例1) SOCKET 1 TX 存储器测试 16位数据总线宽度 & 直接地址模式。

{

/* W5300 Initialize */

MR = MR | 0×0080; // W5300 Soft Reset

Wait for PLL lock-in time (about 10ms)

/* SOCKET Memory Allocation – Instead of using the default size, you can use to your size

in each SOCKET TX/RX memory*/

TMS01R = 0×0808;

TMS23R = 0×0808;

TMS45R = 0×0808;

TMS67R = 0×0808;

RMS01R = 0×0808;

RMS23R = 0×0808;

RMS45R = 0×0808;

RMS67R = 0×0808;

MTYPER = 0x00FF;

/* Set MR(MT) to ‘1’ */

MR = MR | 0×0020;

/* SOCKET n Open */

S1_MR = 0×0001; // sets TCP mode. You can set Sn_MR to other mode

S1_CR = 0×0001; // sets OPEN command

while(S1_CR != 0×0000); // wait until the command is cleared by W5300

// wait until Sn_SSR is changed to SOCK_INIT

while((S1_SSR & 0x00FF) != SOCK_INIT);

/* Test TX Memory of SOCKET n */

// As TX memory size half of SOCKET 1 Host write the test data to S1_TX_FIFOR.

test_data = 0×0000;

for (i = 0; i < 8192/2 ; i++)

{

S1_TX_FIFOR = test_data;

test_data = test_data + 0×0101;

}

// For Verification of SOCKET 1 TX memory, As size half of its Host read the read_data from S1_TX_FIFOR. And then it compares the test_data and the read_data.

test_data = 0×0000;

for(i = 0; i < 8192/2 ; i++)

{

read_data = S1_TX_FIFOR;

if(test_data != read_data) FAIL to verify TX memory of SOCKET 1.

test_data = test_data + 0×0101;

}

/* Close SOCKET n */

S1_CR = 0×0010; //sets CLOSE command

while(S1_CR != 0×0000); //wait unit the command is cleared by W5300

// wait until Sn_SSR is changed to SOCK_CLOSED

while((S1_SSR & 0x00FF) != SOCK_CLOSED);

/* Clear the ‘MT’ bit of MR */

MR = MR & 0xFFDF; // Clear MT bit of MR

}

例2) SOCKET 1 RX存储器测试 8 位数据总线宽度 & 直接地址模式

{

/* W5300 Initialize */

MR1 = MR1 | 0×80; // W5300 Soft Reset

Wait for PLL lock-in time (about 10ms)

/* SOCKET Memory Allocation – Instead of using the default size, you can use to your

memory size in each SOCKET TX/RX memory*/

TMSR0 = 0×08;

TMSR1 = 0×08;

TMSR2 = 0×08;

TMSR4 = 0×08;

TMSR5 = 0×08;

TMSR6 = 0×08;

TMSR7 = 0×08;

RMSR0 = 0×08;

RMSR1 = 0×08;

RMSR2 = 0×08;

RMSR4 = 0×08;

RMSR5 = 0×08;

RMSR6 = 0×08;

RMSR7 = 0×08;

MTYPER0 = 0×00;

MTYPER1 = 0xFF;

/* Set MR(MT) to ‘1’ */

MR1 = MR1 | 0×20;

/* SOCKET n Open */

S1_MR1 = 0×01; // sets TCP mode. You can set Sn_MR to other mode

S1_CR1 = 0×01; // sets OPEN command

while(S1_CR1 != 0×00); // wait until the command is cleared by W5300

// wait until Sn_SSR is changed to SOCK_INIT

while(S1_SSR1 != SOCK_INIT);

/* Test RX Memory of SOCKET n */

// As RX memory size half of SOCKET 1 Host write the test data to S1_RX_FIFOR.

test_data[0] = 0×00;

test_data[1] = 0×00;

for (i = 0; i < 8192/2 ; i++)

{

S1_RX_FIFOR0 = test_data[0];

S1_RX_FIFOR1 = test_data[1];

test_data[0] = test_data[0] + 0×01;

test_data[0] = test_data[0] + 0×01;

}

// For Verification of SOCKET 1 RX memory, As size half of its Host read the read_data from S1_RX_FIFOR. And then it compares the test_data and the read_data.

test_data[0] = 0×00;

test_data[1] = 0×00;

for(i = 0; i < 8192/2 ; i++)

{

read_data[0] = S1_RX_FIFOR0;

read_data[1] = S1_RX_FIFOR1;

if( (test_data[0] != read_data[0]) || (test_data[1] != read_data[1]) )

FAIL to verify RX memory of SOCKET 1.

test_data[0] = test_data[0] + 0×01;

test_data[1] = test_data[1] + 0×01;

}

/* Close SOCKET n */

S1_CR1 = 0×10; //sets CLOSE command

while(S1_CR1 != 0×00); //wait unit the command is cleared by W5300

// wait until Sn_SSR is changed to SOCK_CLOSED

while(S1_SSR1 != SOCK_CLOSED);

/* Clear the ‘MT’ bit of MR */

MR1 = MR1 & 0xDF; // Clear MT bit of MR

}

例3) SOCKET 1 TX 存储器测试 16位数据总线宽度 & 间接地址模式。

{

/* W5300 Initialize */

MR = MR | 0×0080; // W5300 Soft Reset

Wait for PLL lock-in time (about 10ms)

MR = MR | 0×0001; // set IND bit of MR to ‘1’ for indirect address mode

/* SOCKET Memory Allocation – Instead of using the default size, you can use to your

memory size in each SOCKET TX/RX memory*/

IDM_AR = Address Offset of TMSR01R; // 0×0020

IDM_DR = 0×0808;

IDM_AR = Address Offset of TMSR23R; // 0×0022

IDM_DR = 0×0808;

IDM_AR = Address Offset of TMSR45R; // 0×0024

IDM_DR = 0×0808;

IDM_AR = Address Offset of TMSR67R; // 0×0026

IDM_DR = 0×0808;

IDM_AR = Address Offset of RMSR01R; // 0×0028

IDM_DR = 0×0808;

IDM_AR = Address Offset of RMSR23R; // 0x002A

IDM_DR = 0×0808;

IDM_AR = Address Offset of RMSR45R; // 0x002C

IDM_DR = 0×0808;

IDM_AR = Address Offset of RMSR67R; // 0x002E

IDM_DR = 0×0808;

IDM_AR = Address Offset of MTYPER // 0×0030

IDM_DR = 0x00FF;

/* Set MR(MT) to ‘1’ */

MR = MR | 0×0020;

/* SOCKET n Open */

IDM_AR = Address Offset of S1_MR;

IDM_DR = 0×0001; // sets TCP mode. You can set Sn_MR to other mode

IDM_AR = Address Offset of S1_CR;

IDM_DR = 0×0001; // sets OPEN command

while(IDM_DR != 0×0000); // wait until the command is cleared by W5300

// wait until Sn_SSR is changed to SOCK_INIT

IDM_AR = Address Offset of S1_SSR;

while((IDM_DR & 0x00FF) != SOCK_INIT);

/* Test TX Memory of SOCKET n */

// As TX memory size half of SOCKET 1 Host write the test data to S1_TX_FIFOR.

test_data = 0×0000;

IDM_AR = Address offset of S1_TX_FIFOR;

for (i = 0; i < 8192/2 ; i++)

{

IDM_DR = test_data;

test_data = test_data + 0×0101;

}

// For Verification of SOCKET 1 TX memory, As size half of its Host read the read_data from S1_TX_FIFOR. And then it compares the test_data and the read_data.

test_data = 0×0000;

for(i = 0; i < 8192/2 ; i++)

{

read_data = IDM_DR;

if(test_data != read_data) FAIL to verify TX memory of SOCKET 1.

test_data = test_data + 0×0101;

}

/* Close SOCKET n */

IDM_AR = Address Offset of S1_CR

IDM_DR = 0×0010; //sets CLOSE command

while(IDM_DR != 0×0000); //wait unit the command is cleared by W5300

// wait until Sn_SSR is changed to SOCK_CLOSED

IDM_AR = Address Offset of S1_SSR

while((IDM_DR & 0x00FF) != SOCK_CLOSED);

/* Clear the ‘MT’ bit of MR */

MR = MR & 0xFFDF; // Clear MT bit of MR

}

例4) SOCKET 1 RX 存储器测试 8位数据总线宽度 & 间接地址模式。

{

/* W5300 Initialize */

MR1 = MR1 | 0×80; // W5300 Soft Reset

Wait for PLL lock-in time (about 10ms)

MR1 = MR1 | 0×01; // set IND bit of MR to ‘1’ for indirect address mode

/* SOCKET Memory Allocation – Instead of using the default size, you can use to your

memory size in each SOCKET TX/RX memory*/

IDM_AR0 = Higher Address Offset of TMSR01R; // 0×00

IDM_AR1 = Lower Address Offset of TMSR01R; // 0×20

IDM_DR0 = 0×08;

IDM_DR1 = 0×08;

IDM_AR1 = Lower Address Offset of TMSR23R; // 0×22

IDM_DR0 = 0×08;

IDM_DR1 = 0×08;

IDM_AR1 = Lower Address Offset of TMSR45R; // 0×24

IDM_DR0 = 0×08;

IDM_DR1 = 0×08;

IDM_AR1 = Lower Address Offset of TMSR67R; // 0×26

IDM_DR0 = 0×08;

IDM_DR1 = 0×08;

IDM_AR1 = Lower Address Offset of RMSR01R; // 0×28

IDM_DR0 = 0×08;

IDM_DR1 = 0×08;

IDM_AR1 = Lower Address Offset of RMSR23R; // 0x2A

IDM_DR0 = 0×08;

IDM_DR1 = 0×08;

IDM_AR1 = Lower Address Offset of RMSR45R; // 0x2C

IDM_DR0 = 0×08;

IDM_DR1 = 0×08;

IDM_AR1 = Lower Address Offset of RMSR67R; // 0x2E

IDM_DR0 = 0×08;

IDM_DR1 = 0×08;

IDM_AR1 = Lower Address Offset of MTYPER // 0×30

IDM_DR0 = 0×00;

IDM_DR1 = 0xFF;

/* Set MR(MT) to ‘1’ */

MR1 = MR1 | 0×20;

/* SOCKET n Open */

IDM_AR0 = Higher Address Offset of S1_MR; // 0×02

IDM_AR1 = Lower Address Offset of S1_MR; // 0×40

IDM_DR1 = 0×01; // sets TCP mode. You can set Sn_MR to other mode

IDM_AR1 = Lower Address Offset of S1_CR; // 0×42

IDM_DR1 = 0×01; // sets OPEN command

while(IDM_DR1 != 0×00); // wait until the command is cleared by W5300

// wait until Sn_SSR is changed to SOCK_INIT

IDM_AR1 = Lower Address Offset of S1_SSR; // 0×48

while(IDM_DR1 != SOCK_INIT);

/* Test RX Memory of SOCKET n */

// As RX memory size half of SOCKET 1 Host write the test data to S1_RX_FIFOR.

test_data[0] = 0×00;

test_data[1] = 0×00;

IDM_AR1 = Lower Address offset of S1_RX_FIFOR; // 0×70

for (i = 0; i < 8192/2 ; i++)

{

IDM_DR0 = test_data[0];

IDM_DR1 = test_data[1];

test_data[0] = test_data[0] + 0×01;

test_data[1] = test_data[1] + 0×01;

}

// For Verification of SOCKET 1 RX memory, As size half of its Host read the read_data from S1_RX_FIFOR. And then it compares the test_data and the read_data.

test_data[0] = 0×00;

test_data[0] = 0×00;

for(i = 0; i < 8192/2 ; i++)

{

read_data[0] = IDM_DR0;

read_data[1] = IDM_DR1;

if( (test_data[0] != read_data[0]) || (test_data[1] != read_data[1]) )

FAIL to verify RX memory of SOCKET 1.

test_data[0] = test_data[0] + 0×01;

test_data[1] = test_data[1] + 0×01;

}

/* Close SOCKET n */

IDM_AR1 = Lower Address Offset of S1_CR //0×42

IDM_DR1 = 0×10; //sets CLOSE command

while(IDM_DR1 != 0×0000); //wait unit the command is cleared by W5300

// wait until Sn_SSR is changed to SOCK_CLOSED

IDM_AR1 = Lower Address Offset of S1_SSR //0×48

while(IDM_DR1 != SOCK_CLOSED);

/* Clear the ‘MT’ bit of MR */

MR1 = MR1 & 0xDF; // Clear MT bit of MR

}

故障排除指南

当内部存储器测试不能正常进行时，检查如下内容。

• 检查VCC3V3, VCC3A3, VCC1V8, VCC1A8电源
• 检查25MHz工作时钟
• 检查/RESET信号(应该最少保持2us低电平)
• 检查在访问W5300时，/CS、 /RD、 /WR信号是否正确地置低。
• 检查IDR
• 检查寄存器的读/写操作，例如SHAR, GAR, SUBR, SIPR
• 检查MR寄存器的值(DBW, MT, IND bit )
• 检查每个Socket所有的TMSR和RMSR大小的总和应该为128
• 检查每个Socket的TMSR寄存器大小应该为8的倍数
• 检查每个Socket的RMSR寄存器的大小应该为8的倍数
• 检查MTYPER的设定值

在完成了上述检查之后，如果你仍然不能进行存储器测试，按照如下格式转储W5300的所有寄存器，并发送至wiznetbj@wiznettechnology.com

Target Host :Part Name (Datasheet Attachment)

Bus Width :16bit or 8bit

Address Mode :Direct or Indirect

Base Address: 0×08000

0×0000 – 0x00FF Registers Dump

0×0000 : XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

0×0010 : XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

… …

0x00E0 : XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

0x00F0 : XXXX XXXX XXXX XXXX XXXX XXXX XXXX 5300

SOCKET 0 Registers Dump

0×0200 : XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

0×0210 : XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

… …

0×0230 : XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

SOCKET 1 Registers Dump

0×0240 : XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

… …

0×0270 : XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

… …

… …

… …

SOCKET 6 Registers Dump

0×0380 : XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

… …

0x03B0 : XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

SOCKET 7 Registers Dump

0x03C0 : XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

… …

0x03FF : XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

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