/*------------------------------------------------------------------------ *name: *fuction:FPGA第一个实验，四位加法计数器 *other: *version: *author:xufei *description: *time:2017-3-15 ------------------------------------------------------------------------*/ module project(rst_n,cnt,clk); input clk;//没有定义wire或者reg。则默认的是wire型 input rst_n; output[3:0]cnt; reg[3:0] cnt; always@(posedge clk or negedge rst_n) begin if(!rst_n) cnt<=4'd0; else cnt<=cnt+1'b1; end endmodule

//testbench设计：

`timescale 1 ns/ 1 ns module projec_tb(); reg clk; reg rst_n; wire [3:0] cnt; project i1 ( .clk(clk), .cnt(cnt), .rst_n(rst_n) ); initial begin clk=0; forever #10 clk=~clk; end initial begin rst_n=0; #1000; rst_n=1; #5000; $stop; end endmodule 仿真波形