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Part 1. Tutorial for using Microblaze

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In this part we will create and test a MicroBlaze system design using the Embedded Development Kit (EDK).

Step A. Use Base System Builder (BSB) to build a hardware system

? Start XPS
? Using the Base System Builder Wizard and include following hardware components:
? MicroBlaze on Xilinx Spartan-3E Starter Board revision D, running in 50MHz
? 8 KB BRAM, no cache, no FPU
? RS232_DCE (serial port), connected via OPB_RARTLITE, 9600 bit rate, 8 bit data and no parity, use interrupt
? LEDs_8bit, connected via OPB_GPIO
? DDR 32M SDRAM, connected via OPB_DDR
? Add a Timer peripheral, 32 bit width, one timer, use interrupt
? Set stdin and stdout to RS232_DCE (serial port)
? Set all other options to default
? The system generated would also include the following modules:
? Local Memory Bus (LMB) Bus
? On-chip Peripheral Bus (OPB) BUS
? MHS file is your hardware description, MSS is your software description, UCF is the pin mapping to your FPGA.
? All the devices in a Microblaze system are memory mapped. For a single processor, memory addresses for the devices can be generated automatically.
? The xparameter.h file is generated with macros that point to the device addresses. Use the macros in your softwarein your applications so that you don't need to change all the addresses in your application even the device addresses change.
? Build the hardware system using "Hardware" > "Generate Bitstream".

Step B. Hello World

? Click the "Application" tab in the left box and start a new application.
? Set the other application to "inactive"
? Write a hello world application and print a string using the statement

xil_printf("hello world\n"); /* xil_printf() is a light-weight version of printf() */

? Open a hyperterminal and connect it to the serial port. (Programs > Accessories > Communications > HyperTerminal), set it to connect to the serial port (COM1), 9600 bit rate, 8 bit data and no parity
? Connect the Spartan 3E FPGA to the USB port and serial port.
? Build the software and download the bitstream to the FPGA

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