[笔记].一种独立键盘消抖的Verilog写法.[Verilog]
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发表于 2010/6/10 16:12:27
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图1 KEY原理图
图2 LED原理图
key_led.v
01 |
modulekey_led( |
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inputCLOCK_50, |
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inputQ_KEY, |
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input[4:1] KEY, |
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outputreg[4:1] LED |
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); |
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//++++++++++++++++++++++++++++++++++++++ |
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// 获取键值 开始 |
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//++++++++++++++++++++++++++++++++++++++ |
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wire[4:1] key_val;// 键值 |
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key_debounce u0( |
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.i_clk (CLOCK_50), |
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.i_rst_n (Q_KEY), |
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.i_key (KEY), |
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.o_key_val (key_val)// 按下为0，松开为1 |
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); |
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//-------------------------------------- |
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// 获取键值 结束 |
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//-------------------------------------- |
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//++++++++++++++++++++++++++++++++++++++ |
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// 按下键后开关LED 开始 |
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//++++++++++++++++++++++++++++++++++++++ |
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always@ (posedgeCLOCK_50,negedgeQ_KEY) |
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if(!Q_KEY) |
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LED <=4'hF;// 0灭1亮 |
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else |
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case(1'b0) |
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key_val[1] : LED[1] <= ~LED[1]; |
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key_val[2] : LED[2] <= ~LED[2]; |
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key_val[3] : LED[3] <= ~LED[3]; |
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key_val[4] : LED[4] <= ~LED[4]; |
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default: LED <= LED ;// 缺省亮灭情况不变 |
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endcase |
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//-------------------------------------- |
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// 按下键后开关LED 结束 |
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//-------------------------------------- |
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endmodule |
key_debounce.v
01 |
module key_debounce( |
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input i_clk, |
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input i_rst_n, |
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input [4:1] i_key,// 按下为0，松开为1 |
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output reg [4:1] o_key_val// 键值 |
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); |
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//++++++++++++++++++++++++++++++++++++++ |
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reg [4:1] key_samp1, key_samp1_locked; |
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// 将i_key采集至key_samp1 |
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always @ (posedge i_clk, negedge i_rst_n) |
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if(!i_rst_n) |
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key_samp1 <= 4'hF; |
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else |
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key_samp1 <= i_key; |
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// 将key_samp1锁存至key_samp1_locked |
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always @ (posedge i_clk, negedge i_rst_n) |
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if(!i_rst_n) |
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key_samp1_locked <= 4'hF; |
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else |
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key_samp1_locked <= key_samp1; |
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//-------------------------------------- |
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//++++++++++++++++++++++++++++++++++++++ |
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wire [4:1] key_changed1; |
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// 当key_samp1由1变为0时 |
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// key_changed1由0变为1，只维持一个时钟周期 |
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assign key_changed1 = key_samp1_locked & (~key_samp1); |
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//-------------------------------------- |
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//++++++++++++++++++++++++++++++++++++++ |
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reg [19:0] cnt; |
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// 一旦有按键按下，cnt立即被清零 |
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always @ (posedge i_clk, negedge i_rst_n) |
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if(!i_rst_n) |
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cnt <= 20'h0; |
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elseif(key_changed1) |
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cnt <= 20'h0; |
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else |
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cnt <= cnt + 1'b1; |
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//-------------------------------------- |
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//++++++++++++++++++++++++++++++++++++++ |
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reg [4:1] key_samp2, key_samp2_locked; |
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// 只有当按键不变化（不抖动），且维持20ms以上时 |
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// 才将i_key采集至key_samp2 |
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always @ (posedge i_clk, negedge i_rst_n) |
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if(!i_rst_n) |
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key_samp2 <= 4'hF; |
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elseif(cnt == 20'hF_FFFF)// 0xFFFFF/50M = 20.9715ms |
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key_samp2 <= i_key; |
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// 将key_samp2锁存至key_samp2_locked |
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always @ (posedge i_clk, negedge i_rst_n) |
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if(!i_rst_n) |
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key_samp2_locked <= 4'hF; |
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else |
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key_samp2_locked <= key_samp2; |
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//-------------------------------------- |
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//++++++++++++++++++++++++++++++++++++++ |
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wire [4:1] key_changed2; |
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// 当key_samp2由1变为0时 |
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// key_changed2由0变为1，只维持一个时钟周期 |
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assign key_changed2 = key_samp2_locked & (~key_samp2); |
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//-------------------------------------- |
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//++++++++++++++++++++++++++++++++++++++ |
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// 每次按键稳定后，输出键值 |
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// 按下为0，松开为1 |
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always @ (posedge i_clk, negedge i_rst_n) |
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if(!i_rst_n) |
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o_key_val <= 4'hF; |
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else |
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o_key_val <= ~key_changed2; |
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//-------------------------------------- |
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endmodule |
