[笔记].算法 - 乘积累加器.[Verilog]
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发表于 2010/8/24 12:29:15
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出自Quartus II自带模板。
1. 无符号数乘积累加器
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moduleunsigned_multiply_accumulate |
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#(parameterWIDTH=8) |
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( |
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inputclk, aclr, clken, sload, |
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input[WIDTH-1:0] dataa, |
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input[WIDTH-1:0] datab, |
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outputreg[2*WIDTH-1:0] adder_out |
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); |
09 |
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// Declare registers and wires |
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reg[WIDTH-1:0] dataa_reg, datab_reg; |
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regsload_reg; |
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reg[2*WIDTH-1:0] old_result; |
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wire[2*WIDTH-1:0] multa; |
15 |
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// Store the results of the operations on the current data |
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assignmulta = dataa_reg * datab_reg; |
18 |
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// Store the value of the accumulation (or clear it) |
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always@ (adder_out, sload_reg) |
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begin |
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if(sload_reg) |
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old_result <= 0; |
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else |
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old_result <= adder_out; |
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end |
27 |
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// Clear or update data, as appropriate |
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always@ (posedgeclkorposedgeaclr) |
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begin |
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if(aclr) |
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begin |
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dataa_reg <= 0; |
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datab_reg <= 0; |
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sload_reg <= 0; |
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adder_out <= 0; |
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end |
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elseif(clken) |
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begin |
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dataa_reg <= dataa; |
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datab_reg <= datab; |
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sload_reg <= sload; |
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adder_out <= old_result + multa; |
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end |
45 |
end |
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endmodule |
2. 有符号数乘积累加器
01 |
modulesigned_multiply_accumulate |
02 |
#(parameterWIDTH=8) |
03 |
( |
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inputclk, aclr, clken, sload, |
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inputsigned [WIDTH-1:0] dataa, |
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inputsigned [WIDTH-1:0] datab, |
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outputregsigned [2*WIDTH-1:0] adder_out |
08 |
); |
09 |
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// Declare registers and wires |
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regsigned [WIDTH-1:0] dataa_reg, datab_reg; |
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regsload_reg; |
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regsigned [2*WIDTH-1:0] old_result; |
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wiresigned [2*WIDTH-1:0] multa; |
15 |
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// Store the results of the operations on the current data |
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assignmulta = dataa_reg * datab_reg; |
18 |
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// Store (or clear) old results |
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always@ (adder_out, sload_reg) |
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begin |
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if(sload_reg) |
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old_result <= 0; |
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else |
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old_result <= adder_out; |
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end |
27 |
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// Clear or update data, as appropriate |
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always@ (posedgeclkorposedgeaclr) |
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begin |
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if(aclr) |
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begin |
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dataa_reg <= 0; |
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datab_reg <= 0; |
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sload_reg <= 0; |
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adder_out <= 0; |
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end |
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elseif(clken) |
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begin |
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dataa_reg <= dataa; |
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datab_reg <= datab; |
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sload_reg <= sload; |
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adder_out <= old_result + multa; |
44 |
end |
45 |
end |
46 |
endmodule |
3. 四乘积累加器
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modulesum_of_four_multiply_accumulate |
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#(parameterINPUT_WIDTH=18,parameterOUTPUT_WIDTH=44) |
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( |
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inputclk, ena, |
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input[INPUT_WIDTH-1:0] dataa, datab, datac, datad, |
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input[INPUT_WIDTH-1:0] datae, dataf, datag, datah, |
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outputreg[OUTPUT_WIDTH-1:0] dataout |
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); |
09 |
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// Each product can be up to 2*INPUT_WIDTH bits wide. |
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// The sum of four of these products can be up to 2 bits wider. |
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wire[2*INPUT_WIDTH+1:0] mult_sum; |
13 |
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// Store the results of the operations on the current inputs |
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assignmult_sum = (dataa * datab + datac * datad) + (datae * dataf + datag * datah); |
16 |
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// Store the value of the accumulation |
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always@ (posedgeclk) |
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begin |
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if(ena == 1) |
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begin |
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dataout <= dataout + mult_sum; |
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end |
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end |
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endmodule |
4. 带异步复位的四乘积累加器
01 |
modulesum_of_four_multiply_accumulate_with_asynchronous_reset |
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#(parameterINPUT_WIDTH=18,parameterOUTPUT_WIDTH=44) |
03 |
( |
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inputclk, ena, aclr, |
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input[INPUT_WIDTH-1:0] dataa, datab, datac, datad, |
06 |
input[INPUT_WIDTH-1:0] datae, dataf, datag, datah, |
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outputreg[OUTPUT_WIDTH-1:0] dataout |
08 |
); |
09 |
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// Each product can be up to 2*INPUT_WIDTH bits wide. |
11 |
// The sum of four of these products can be up to 2 bits wider. |
12 |
wire[2*INPUT_WIDTH+1:0] mult_sum; |
13 |
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// Store the results of the operations on the current inputs |
15 |
assignmult_sum = (dataa * datab + datac * datad) + (datae * dataf + datag * datah); |
16 |
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// Store the value of the accumulation |
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always@ (posedgeclk) |
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begin |
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if(ena == 1) |
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begin |
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dataout <= ((aclr == 1) ? 0 : dataout) + mult_sum; |
23 |
end |
24 |
end |
25 |
endmodule |
