[笔记].算法 - 乘法器.[Verilog]
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发表于 2010/8/24 9:53:53
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出自Quartus II自带模板。
1. 无符号数乘法器
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moduleunsigned_multiply |
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#(parameterWIDTH=8) |
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( |
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input[WIDTH-1:0] dataa, |
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input[WIDTH-1:0] datab, |
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output[2*WIDTH-1:0] dataout |
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); |
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assigndataout = dataa * datab; |
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endmodule |
2. 有符号数乘法器
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modulesigned_multiply |
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#(parameterWIDTH=8) |
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( |
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inputsigned [WIDTH-1:0] dataa, |
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inputsigned [WIDTH-1:0] datab, |
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output[2*WIDTH-1:0] dataout |
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); |
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assigndataout = dataa * datab; |
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endmodule |
3. 带输入输出寄存器的无符号数乘法器
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moduleunsigned_multiply_with_input_and_output_registers |
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#(parameterWIDTH=8) |
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( |
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inputclk, |
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input[WIDTH-1:0] dataa, |
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input[WIDTH-1:0] datab, |
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outputreg[2*WIDTH-1:0] dataout |
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); |
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// Declare input and output registers |
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reg[WIDTH-1:0] dataa_reg; |
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reg[WIDTH-1:0] datab_reg; |
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wire[2*WIDTH-1:0] mult_out; |
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// Store the result of the multiply |
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assignmult_out = dataa_reg * datab_reg; |
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// Update data |
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always@ (posedgeclk) |
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begin |
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dataa_reg <= dataa; |
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datab_reg <= datab; |
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dataout <= mult_out; |
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end |
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endmodule |
4. 带输入输出寄存器的有符号数乘法器
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modulesigned_multiply_with_input_and_output_registers |
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#(parameterWIDTH=8) |
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( |
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inputclk, |
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inputsigned [WIDTH-1:0] dataa, |
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inputsigned [WIDTH-1:0] datab, |
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outputregsigned [2*WIDTH-1:0] dataout |
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); |
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// Declare input and output registers |
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regsigned [WIDTH-1:0] dataa_reg; |
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regsigned [WIDTH-1:0] datab_reg; |
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wiresigned [2*WIDTH-1:0] mult_out; |
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// Store the result of the multiply |
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assignmult_out = dataa_reg * datab_reg; |
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// Update data |
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always@ (posedgeclk) |
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begin |
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dataa_reg <= dataa; |
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datab_reg <= datab; |
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dataout <= mult_out; |
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end |
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endmodule |
5. 复数乘法器
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modulemultiplier_for_complex_numbers |
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#(parameterWIDTH=18) |
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( |
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inputclk, ena, |
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inputsigned [WIDTH-1:0] dataa_real, dataa_img, |
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inputsigned [WIDTH-1:0] datab_real, datab_img, |
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outputregsigned [2*WIDTH-1:0] dataout_real, dataout_img |
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); |
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always@ (posedgeclk) |
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begin |
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if(ena == 1) |
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begin |
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dataout_real = dataa_real * datab_real - dataa_img * datab_img; |
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dataout_img = dataa_real * datab_img + datab_real * dataa_img; |
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end |
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end |
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endmodule |
