[笔记].算法 - 加法器.[Verilog]
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发表于 2010/8/23 16:46:05
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1 有符号数加法器
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modulesigned_adder |
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#(parameterWIDTH=16) |
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( |
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inputsigned [WIDTH-1:0] dataa, |
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inputsigned [WIDTH-1:0] datab, |
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inputcin, |
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output[WIDTH:0] result |
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); |
09 |
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assignresult = dataa + datab + cin; |
11 |
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endmodule |
2 无符号数加法器
01 |
moduleunsigned_adder |
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#(parameterWIDTH=16) |
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( |
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input[WIDTH-1:0] dataa, |
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input[WIDTH-1:0] datab, |
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inputcin, |
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output[WIDTH:0] result |
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); |
09 |
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assignresult = dataa + datab + cin; |
11 |
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endmodule |
3 有符号数加法/减法器
01 |
modulesigned_adder_subtractor |
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#(parameterWIDTH=16) |
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( |
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inputsigned [WIDTH-1:0] dataa, |
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inputsigned [WIDTH-1:0] datab, |
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inputadd_sub,// if this is 1, add; else subtract |
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inputclk, |
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outputreg[WIDTH:0] result |
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); |
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always@ (posedgeclk) |
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begin |
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if(add_sub) |
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result <= dataa + datab; |
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else |
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result <= dataa - datab; |
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end |
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endmodule |
无符号数加法/减法器
01 |
moduleunsigned_adder_subtractor |
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#(parameterWIDTH=16) |
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( |
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input[WIDTH-1:0] dataa, |
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input[WIDTH-1:0] datab, |
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inputadd_sub,// if this is 1, add; else subtract |
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inputclk, |
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outputreg[WIDTH:0] result |
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); |
10 |
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always@ (posedgeclk) |
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begin |
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if(add_sub) |
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result <= dataa + datab; |
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else |
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result <= dataa - datab; |
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end |
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endmodule |
二进制流水线加法树
01 |
modulepipelined_binary_adder_tree |
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#(parameterWIDTH=16) |
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( |
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input[WIDTH-1:0] A, B, C, D, E, |
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inputclk, |
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output[WIDTH-1:0] out |
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); |
08 |
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wire[WIDTH-1:0] sum1, sum2, sum3, sum4; |
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reg[WIDTH-1:0] sumreg1, sumreg2, sumreg3, sumreg4; |
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always@ (posedgeclk) |
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begin |
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sumreg1 <= sum1; |
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sumreg2 <= sum2; |
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sumreg3 <= sum3; |
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sumreg4 <= sum4; |
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end |
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// 2-bit additions |
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assignsum1 = A + B; |
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assignsum2 = C + D; |
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assignsum3 = sumreg1 + sumreg2; |
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assignsum4 = sumreg3 + E; |
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assignout = sumreg4; |
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endmodule |
