相信很多学过FPGA的同学都接触过这个按理-交通灯控制，只是我的这个是基于Xilinx XC2S200的，别有一番风味。

我还是先说这个项目的过程吧：

1实验原理

在此实验中，我们要做的就是基于状态机设计一个十字路口交通灯控制器。其示意图如下：

A方向和B方向各设红、黄、绿三盏灯，三种灯按合理的顺序亮灭，以完成交通控制的功能。

利用实验台所提供的按键开关模拟南北方向和东西方向的车辆探测器（sensor1, sensor2），按下按键则表示该方向有车辆需要通过，利用实验台的发光二级管模拟两个方向上的红、绿、黄灯(red1, green1, yellow1; red2 green2 yellow2)，由一片可编程逻辑芯片控制交通灯，该芯片运行的时钟(clk)由实验台提供，编程计时(clock)。当仅有一个方向上有车辆需要通过，则该方向上绿灯长亮，当两个方向上均有车辆通过的时候，交通灯切换指示。

实现状态机的转换图：

2源代码

1.Verilog源代码，TrafficLight.v

module traffic(clk,snCar,ewCar,

snRed,snYellow,snGreen,

ewRed,ewYellow,ewGreen);

input snCar, ewCar,clk;

output reg snRed;

output reg snYellow;

output reg snGreen;

output reg ewRed;

output reg ewYellow;

output reg ewGreen;

reg [5:0] state;

reg [15:0] timer1;

reg [7:0] timer2;

reg time1Up,time2Up;

reg enableTime1,enableTime2;

parameter TIME1NUM=2000, TIME2NUM=200;

parameter EWGREEN=5'b00000, EWGREENWAIT=5'b00001;

parameter EWYELLOW=5'b00010;

parameter SNGREEN=5'b00100, SNGREENWAIT=5'b01000;

parameter SNYELLOW=5'b10000;

always @(posedge clk)

if (enableTime1)

if (timer1==TIME1NUM) time1Up<=1;

else timer1<=timer1+1;

else

begin

timer1<=0;

time1Up<=0;

end

always @(posedge clk)

if (enableTime2)

if (timer2==TIME2NUM) time2Up<=1;

else timer2<=timer2+1;

else

begin

timer2<=0;

time2Up<=0;

end

always @(state)

case (state)

EWGREEN:

if (time1Up) state<=EWGREENWAIT;

EWGREENWAIT:

if (snCar) state<=EWYELLOW;

EWYELLOW:

if (time2Up) state<=SNGREEN;

SNGREEN:

if (time1Up) state<=SNGREENWAIT;

SNGREENWAIT:

if (ewCar) state<=SNYELLOW;

SNYELLOW:

if (time2Up) state<=EWGREEN;

default: state<=EWGREEN;

endcase

always @(posedge clk)

case (state)

EWGREEN:

begin

enableTime1<=1;

enableTime2<=0;

ewGreen<=1;

ewYellow<=0;

ewRed<=0;

snGreen<=0;

snYellow<=0;

snRed<=1;

end

EWGREENWAIT:

enableTime1<=0;

EWYELLOW:

begin

enableTime2<=1;

ewGreen<=0;

ewYellow<=1;

ewRed<=0;

snGreen<=0;

snYellow<=0;

snRed<=1;

end

SNGREEN:

begin

enableTime2<=0;

enableTime1<=1;

ewGreen<=0;

ewYellow<=0;

ewRed<=1;

snGreen<=1;

snYellow<=0;

snRed<=0;

end

SNGREENWAIT:

enableTime1<=0;

SNYELLOW:

begin

enableTime2<=1;

ewGreen<=0;

ewYellow<=0;

ewRed<=1;

snGreen<=0;

snYellow<=1;

snRed<=0;

end

endcase

endmodule

2.引脚分配源代码，TrafficLight.ucf

net rst loc = p57;

net clk loc = p80;

net snCar loc = p126;

net ewCar loc = p123;

net snRed loc = p205;

net snYellow loc = p203;

net snGreen loc = p201;

net ewRed loc = p206;

net ewYellow loc = p204;

net ewGreen loc = p202;

重要说明：

1.使用Xilinx XC2S200型FPGA器件设计实现

2.使用电子EDA实验开发系统的通用IO口，将静态LED的段码值由高往低送。

3.使用Xinlix ISE 6.3软件进行Verilog HDL开发

FPGA的孩纸们伤不起啊，跟我一起重温经典吧。。。。