在高速数据采集和处理系统中，随着采样数据量的增大及信息处理任务的增加，对数据传送的要求也越来越高。在系统或模块间如果没有能够高速传送数据的接口，则在数据传送时极易造成瓶颈堵塞现象，从而影响整个系统对数据的处理能力。所以，高速并行数据接口的研制在信息处理系统中占有非常重要的地位。

由于FPGA的容量有限，对于快速的视频采集系统来说，需要快速切换数据来进行处理和显示，利用FPGA内部的资源可以轻松搭建两个1Kb字节的双口SRAM，减少外围器件配置， 通过端口的“乒乓操作”提高数据处理速度，进而提高数据传输速度。

// synopsys translate_off

`timescale 1 ps / 1 ps

// synopsys translate_on

module RAM2 (

data_a,

wren_a,

address_a,

data_b,

address_b,

wren_b,

clock_a,

clock_b,

q_a,

q_b);

input [7:0] data_a;

input wren_a;

input [9:0] address_a;

input [7:0] data_b;

input [9:0] address_b;

input wren_b;

input clock_a;

input clock_b;

output [7:0] q_a;

output [7:0] q_b;

wire [7:0] sub_wire0;

wire [7:0] sub_wire1;

wire [7:0] q_a = sub_wire0[7:0];

wire [7:0] q_b = sub_wire1[7:0];

altsyncram altsyncram_component (

.wren_a (wren_a),

.clock0 (clock_a),

.wren_b (wren_b),

.clock1 (clock_b),

.address_a (address_a),

.address_b (address_b),

.data_a (data_a),

.data_b (data_b),

.q_a (sub_wire0),

.q_b (sub_wire1)

// synopsys translate_off

,

.aclr0 (),

.aclr1 (),

.addressstall_a (),

.addressstall_b (),

.byteena_a (),

.byteena_b (),

.clocken0 (),

.clocken1 (),

.rden_b ()

// synopsys translate_on

);

defparam

altsyncram_component.intended_device_family = "Cyclone II",

altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",

altsyncram_component.width_a = 8,

altsyncram_component.widthad_a = 10,

altsyncram_component.numwords_a = 1024,

altsyncram_component.width_b = 8,

altsyncram_component.widthad_b = 10,

altsyncram_component.numwords_b = 1024,

altsyncram_component.lpm_type = "altsyncram",

altsyncram_component.width_byteena_a = 1,

altsyncram_component.width_byteena_b = 1,

altsyncram_component.outdata_reg_a = "UNREGISTERED",

altsyncram_component.outdata_aclr_a = "NONE",

altsyncram_component.outdata_reg_b = "UNREGISTERED",

altsyncram_component.indata_reg_b = "CLOCK1",

altsyncram_component.address_reg_b = "CLOCK1",

altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1",

altsyncram_component.outdata_aclr_b = "NONE",

altsyncram_component.clock_enable_input_a = "BYPASS",

altsyncram_component.clock_enable_output_a = "BYPASS",

altsyncram_component.clock_enable_input_b = "BYPASS",

altsyncram_component.clock_enable_output_b = "BYPASS",

altsyncram_component.power_up_uninitialized = "FALSE";

endmodule

（转自Altera FPGA小组，作者：youzizhile ）