IIC 程序设计
0赞工程说明
1。源文件保存在src目录，QII的工程文件保存在Proj目录；
2。程序实现的功能是通过I2C配置SAA7113芯片,;
3. 编译方法:
首先打开工程文件,双击SAA_ROM模块;
其中配置文件(MIF)的目录需要根据需要来修改;按两次Next,出现
Do you want to specify the initial content of memery?选项,指定saa7113.mif所在目录.
确定mif文件指定到D:\RedLogic\RCII_samples\VideoCap_RCE02\Src\Configure目录下的saa7113.mif文件.
4。 根据输出时序,设计采集程序.
I2C设计实例：
i2c命令产生逻辑，采用 状态机方式实现。
module i2c_cmd(clk,rst,rom_data,busy,
rom_addr,i2c_data_t,cmd_stop,cmd_start,cmd_send,
execute,i2c_w_finish
);
//Io defination
input clk,rst,busy;//时钟，复位，忙信号
input [7:0] rom_data;//存储器数据
output cmd_stop,cmd_start,cmd_send,execute,i2c_w_finish;//命令控制，包括停止，开始，发送，执行，结束
output[6:0] rom_addr;//存储器地址
output[7:0] i2c_data_t;//i2C数据
reg cmd_stop,cmd_start,cmd_send,execute,i2c_w_finish;
reg[6:0] rom_addr;
reg[7:0] i2c_data_t;
//Internal Reg
parameter GEN_S='H1, S_WAIT='H2,
SUBADDR='H5, SUBADDR_ACK='H6, DATA='H7, DATA_ACK='H8,
GEN_P='H9, P_WAIT='HA, IDLE='HB ,I2C_W_OK='HC,HALT='HD,CREATE_CHIP_RST='HE;
reg [3:0] STATE;
reg group_index;
always @ (posedge clk)
begin
if(!rst)
begin
STATE<=IDLE;
cmd_stop<=0;
cmd_start<=0;
cmd_send<=0;
execute<=0;
rom_addr<='b0;
i2c_data_t<='b0;
group_index<='b0;
i2c_w_finish<=0;
end
else
case (STATE)
IDLE: begin//空闲状态
STATE<=GEN_S;
end
GEN_S:begin//开始
i2c_data_t<='h4A; //Saa7113 Write Address
cmd_start<=1;
execute<=1;
if(busy)
STATE<=S_WAIT;
else
STATE<=GEN_S;
end
S_WAIT:begin//等待处理完成
cmd_start<=0;
execute<=0;
if (!busy)
STATE<=SUBADDR; //SLAVE_W;
else
STATE<=S_WAIT;
end
SUBADDR://寄存器地址
begin
i2c_data_t<=group_index? 'h40 : 'h01; //Start of Group Address
cmd_send<=1;
execute<=1;
if(busy)
STATE<=SUBADDR_ACK;
else
STATE<=SUBADDR;
end
SUBADDR_ACK:
begin
cmd_send<=0;
execute<=0;
rom_addr<=group_index? 'h40 : 'h01;
if (!busy)
STATE<=DATA;
else
STATE<=SUBADDR_ACK;
end
DATA: begin
i2c_data_t<=rom_data; //Data
cmd_send<=1;
execute<=1;
if(busy)
STATE<=DATA_ACK;
else
STATE<=DATA;
end
DATA_ACK:
begin
cmd_send<=0;
execute<=0;
if (!busy)
begin
if( ((!group_index) & (rom_addr>='h17)) | ((group_index) & (rom_addr>='h5f)) )
STATE<=GEN_P;
else
begin
rom_addr<=rom_addr+1;
STATE<=DATA;
end
end
else
STATE<=DATA_ACK;
end
GEN_P:begin
cmd_stop<=1;
execute<=1;
if(busy)
STATE<=P_WAIT;
else
STATE<=GEN_P;
end
P_WAIT:begin
cmd_stop<=0;
execute<=0;
if (!busy)
STATE<=I2C_W_OK;
else
STATE<=P_WAIT;
end
I2C_W_OK:
begin
if (group_index)
begin
STATE<=HALT;
end
else
begin
group_index<=1;
STATE<=GEN_S;
end
end
HALT: begin
STATE<=HALT;
i2c_w_finish<=1;
end
default: STATE<=IDLE;
endcase
end
endmodule
TITLE "I2C Controller";
PARAMETERS
(
DIVISOR = 25
);
（转自Altera FPGA小组，作者：youzizhile ）
