Altera Forum精彩问答汇总

发表于 2010/5/4 10:34:47 阅读（3179）

坛中一日，人间数年！

I can't afford losing any of this kind of invaluable information anymore! It is not too late if I start reading and collecting them from now on. I will look the threads through everyday as I do with my Hotmail E-mails and EETimes RSSs.

It's all about Timing：

Sun Nov 08 2009 09:35:01 GMT+0800Timing Analysis of a Source Synchronous Interface Using ALTLVDSThanks again! Kwalt.

Wed Nov 4 2009 21:01:49 UTC+0800Slack:Not operational: Clock Skew>Data Delay ...No answers yet. Do an experiment myself.

Wed Nov 4 2009 20:46:41 UTC+0800Timing constraints for ALTLVDS I/O

Wed Nov 4 2009 20:44:29 UTC+0800Constraining SOPC Builder designs using TimeQuest
Wed Nov 04 2009 00:26:23 GMT-0800 (Pacific Standard Time)Instantiate primitive DFF with an an inverted clock input"the inverter get absorbed into the LAB clock inversion and there is no clock skew and no timing issues"
Wed Nov 04 2009 00:12:59 GMT-0800 (Pacific Standard Time)Timing Analysis of Internally Generated Clocks in Timequestkwalt, How many thanks I owe you!
Wed Nov 04 2009 00:11:35 GMT-0800 (Pacific Standard Time)The inconsistent results of the Timequest
Wed Nov 04 2009 00:08:23 GMT-0800 (Pacific Standard Time)How to Constraint Source-Synchronous Double-Data Rate Interfaces
Wed Nov 04 2009 00:07:33 GMT-0800 (Pacific Standard Time)Recovery timing errors using clock crossing bridge
Wed Nov 04 2009 00:04:29 GMT-0800 (Pacific Standard Time)set_clock_groups notes
Wed Nov 04 2009 00:02:47 GMT-0800 (Pacific Standard Time)case analysis and false path issues
Wed Nov 04 2009 00:00:51 GMT-0800 (Pacific Standard Time)Timequest: WHY?Pros and Cons!
Tue Nov 03 2009 23:40:59 GMT-0800 (Pacific Standard Time)Centering the Clock in the Data Valid Window for Source Syncrhonous Inputs
Tue Nov 03 2009 23:39:04 GMT-0800 (Pacific Standard Time)Timing Analysis of Source Synchronous Outputs
Tue Nov 03 2009 23:38:08 GMT-0800 (Pacific Standard Time)Implementing a Source Synchronous Interface between Altera FPGAs v2.0
Tue Nov 03 2009 23:24:57 GMT-0800 (Pacific Standard Time)Clock setup and hold slack explained
Tue Nov 03 2009 23:11:44 GMT-0800 (Pacific Standard Time)Applying multicycle assignments
Sun Nov 01 2009 17:17:32 GMT+0800signal transfer in different clock domains
Sun Nov 01 2009 16:53:26 GMT+0800Implementation and Timing of Reset Circuits
Sun Nov 01 2009 16:46:41 GMT+0800Timequest & Output delay problem"I've found it easy to totally get wrapped up into equations and lost in the details."
Sun Nov 01 2009 16:39:19 GMT+0800PLL Compensation warningStill not quite clear about this. Need to do a experiment myself.
Sun Nov 01 2009 16:37:35 GMT+0800I need a low jitter clock mux in logic cells"We then use a phase-frequency detector to track the difference between the CRU clock and the reference clock. We can then tune our reference clock to match the frequency of the CRU clock." Have I missed out similar in-house designs?
Sun Nov 01 2009 16:36:16 GMT+0800Understanding Recovery and Removal in TimeQuestWill study it carefully when I have time.
Sun Nov 01 2009 16:35:14 GMT+0800Ripple and gated clocks: clock dividers, clock muxes, and other logic-driven clocksThis one really helps. It guided my recent work to a success!

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