4.4.2Design Reviews

Design reviews are very important to the FPGA design process. Reviews should be multidisciplinary and include mechanical and software engineers in addition to hardware and FPGA engineers.The requirements review should be thorough but not overly formal. The objective of the review is the make sure that everyone is aware of the requirements from the earliest stages of the design to avoid design rework later in the design cycle. The following lists provide a summarized list of those objectives, factors and topics relevant to a design review.

Design Review Objectives

• [endif]-->Present how critical and difficult design requirements and objectives are being met and alternative implementations which were evaluated.
• <> [endif]-->Consider full or partial verification matrix or table to present how critical design requirements are being met
• Record, track and resolve issues identified during the review
• Identify critical design issues and challenges (risk)
• Focus on high-risk circuit, function and interface implementations
• Present critical Finite State Machines (FSMs)
• Identify signals targeted for global resources
• Detailed clock implementation overview
• [endif]-->Focus on synchronous design implementation
• <> [endif]-->How high-speed signals and buses will be resynchronized at the FPGA I/O blocks
• [endif]-->Present mechanical considerations (device size and height, likely number of board layers, proposed access to FPGA configuration and test headers in deliverable product configuration, clearances for device rework)
• Design power-up sequence, timing and how all I/O power-up, configuration and reset states will interact with the board-level circuitry
• [endif]-->I/O signals requiring special configuration (level, slew, threshold, termination)
• [endif]-->Design configuration control plan and procedure
• Initial board power-up plan (proposed FPGA minimum functionality)
• Design testing plan (debug and verification)
• Design block simulation plan

Design Review Topics

• [endif]-->Identify nets for global distribution
• <> Identify and characterize high-performance signals (differential signal pairs, board level routing concerns, package pin assignment limitations, controlled impedance, guard bands, distance from high-noise sources, signal termination architecture)
• Simultaneous Switching Outputs (SSO) consideration
• Potential device placement and orientation
• Data flow: how will critical signals and buses enter and exit the FPGA device and route through the FPGA?
• [endif]-->I/O placement/selection effects on board routing
• I/O placement/selection relationship to I/O banks and SSO considerations
• I/O characteristics (drive strength, differential pairs, placement, I/O mode, slew rate, need for assignment to dedicated or special function pin)
• I/O signal state effect on circuitry external to FPGA device before and during configuration and during FPGA special conditions such as device reset
• [endif]-->Need for worst-case simulation (process, temperature, etc.)

4.4.2设计评审

设计评审对FPGA设计过程是非常重要的。评审应该博采众家之长，应该是跨部门的，除 硬件和FPGA工程师之外，还应该包括机械设计和软件工程师。需求评审应该详尽彻底，但是不必过于正式。需求评审的目的是确保每个人在设计的最初阶段就清楚设计需 求，避免设计后期的返工。下面提供了与设计评审的目的、要素和主题相关的三个概要清单。

设计评审目的清单

< >向设计团队的 全体成员介绍设计需求，讨论自上次的正式设计评审以来的需求更新。 介绍关键的设计需求和困难的设计目标是如何满足的，介绍已评估过的可供替代的实现方案。 评审对于及时发现在将来会变成难题的问题是关键的。缺乏足够时间做准备和进行评审的项目很可能会遇到 不必要的延期。 介绍当前的设 计状况、设计更新、设计决定，设计结构和需求更新 考虑 通过全面的或部分的验证矩阵或表格来介绍关键的设计需求是如何得到满足的。 应该包括设计框图 记录、跟踪和解决评审过程中发现的问题 确定关键的设计问题和挑战（风险） 专注于高风险的电路、功能和接口的实现 介绍关键的有限状态机（FSM） 确定会占用全局资源的信号 逐条简介每一个时 钟的实现方案 专注于同步时钟实现方式 标出任何不可避免的异步电路，额外关注其功能实现 评审全部的关键设计接口和时钟域边界（跨时钟域信号同步） 高速信号和总线在FPGA的I/O模块中是如何得到同步的 介绍功耗和发热估计 介绍机械结构方面的考虑（元件的大小和高度、可能的PCB层数、在可交付的产品外廓上为FPGA配置和测试插头预留的插口、PCB板上为拆卸和重焊预留的器件间隙） 上电复位方案 器件启动顺序和时序，FPGA的I/O引脚的上电、配置和复位状态是如何与电路板上的其它器件相互配合的 需要特殊配置的I/O信号（信号电平、上升斜率、门限和端接） 故障、错误和警告的监测和相应的指示 配置管理计划和步骤 集成计划（元器件级和板级） 首次电路板上电计划（在首次上电测试中FPGA需要提供的最小/最基本功能） 设计测试计划（调试和验证） 设计模块仿真计划 确认用于全局 分布的网络 详细的时钟实现分析（布线结果、全局布线资 源的使用情况、速度、分布、抖动、反馈路径和建议的约束） 确认进出FPGA的关键信号和总线 确认和描述高性能信号的特 征（差分信号对、板级布线考虑、器件封装对引脚分配的限制、受控阻抗、信号线之间的保护间隔、信号线与高噪声源的距离、信号端接方式） 对同步翻转输出（SSO）产生的影响的考虑 可能的器件摆放位置和方向 数据流：关键的信号和总线是如何进出FPGA器件的，在FPGA内部是如何布线的？ I/O的布局位置/位置选取对板级布线的影响 I/O的布局位置/位置选取对FPGA内部信号布线的影响 I/O的布局位置/位置选取与I/O组选取和SSO影响的关系 I/O的特征（驱动强度、差分对、布局、输入输出模式、上升斜率、分配到专用或特殊引脚的需要） 配置加载前、加载过程中和器件复位过程中，I/O信号的状态对FPGA器件外部电路的影响 对最差工作情况进行仿真的需要（加工过程、工作温度等）