在Aldec的AVM Seminar中，我最感兴趣的是AVMS VI-04 - Automating Testbench Tasks with Tcl。这个Seminar讨论的内容和我当前的工作重点是重合的。

研讨会定于Thursday 8/07/2008, 11:00 AM (Pacific Daylight Time)开始。我虽然提前进行了注册，第二天又是休息日，怎奈北京时间凌晨2点还是太晚了些，到底没坚持到开始。好在 9号晚上看完比赛回到家，录好的研讨会回放已经上网了，riple赶紧把它down了下来。

研讨会的内容简介如下：

Abstract: Many EDA tools (including Riviera-PRO) incorporate a Tcl shell that enables their actions to be automated by a suitable script. This is particularly useful for repetitive tasks such as running regression tests or a series of related simulations. This presentation introduces the Tcl language and shows how powerful scripts can be quickly put together by someone knowing only a handful of language constructs. It shows how common tasks such as running simulations and extracting results may be automated by a script and how to make such scripts reusable.

从上面这段文字看来，Tcl在仿真过程自动化中可以起到至关重要的作用。这一点是得益于EDA工具对Tcl的支持和扩展。记得我在学 习Tcl系列文章的开篇中说：“学会了Tcl，自己就能EDA了”。现在看来，当初的判断和选择是正确的。

看完了研讨会回放，我既找到了支持当前工作方案的有力论据，还学到了几个既巧妙又不失规范的操作。真对得起我这几周以来的期待！

摘抄研讨会的Summary如下：

Very simple Tcl scripting can make your life easier:
consistent compilation flow
making lists of related files
Just a little more understanding of Tcl can yield big benefits:
sophisticated management of testbench vector and log files
automated interaction with other tools (revision control, ...)
Easy access to Tcl scripting in the Aldec simulators
All simulator commands and variables accessible from Tcl
Breakpoint, force, examine commands are well suited to scripting-automate repetitive actions

从研讨会中，我发现了一个非常有趣的现象：Aldec仿真工具中提供的命令与Modelsim提供的命令竟然如出一辙。do、force、 examine、when这样的关键命令和$1、$2这样的.do文件参数传递方式都是一模一样的。

向业界的老大哥看齐对用户和工具商应该都是大有好处的。

相关链接：

Wed Aug 27 2008 12:46:40 UTC+0800TCL Drives C Drives SystemVerilog- An Overview

Wed Aug 27 2008 12:46:49 UTC+0800Using VMM, DPI, and TCL to Leverage Verification and Enable Early Testing, Emulation, and Validation- The Details