Quartus II 8.0中新添加了这个“系统控制台”功能。从SOPC Builder的Tools-〉Launch System Console就可以打开。下面是欢迎界面：

Welcome to Altera's System Console

This Tcl console provides access to the hardware modules instantiated in your
FPGA. You can use the System Console for all of the following purposes:

* To start, stop, or step a Nios II processor
* To read or write Avalon Memory-Mapped (Avalon-MM) slaves using special
masters
* To sample the SOPC system clock as well as system reset signal
* To run JTAG loopback tests to analyze board noise problems
* To shift arbitrary instruction register and data register values to
instantiated system level debug (SLD) nodes

In addition, the directory $QUARTUS_ROOTDIR/sopc_builder/system_console_macros
contains Tcl files that provide miscellaneous utilities and examples of how to
access the functionality provided. You can include those macros in your
scripts by issuing Tcl source commands.

下面是命令列表：

Get help on any of the following commands:

add_help
bytestream_receive
bytestream_send
close_service
elf_download
get_service_paths
get_service_types
help
is_service_open
jtag_debug_loop
jtag_debug_reset_system
jtag_debug_sample_clock
jtag_debug_sample_reset
jtag_debug_sense_clock
master_read_16
master_read_32
master_read_8
master_read_memory
master_write_16
master_write_32
master_write_8
master_write_memory
open_service
processor_get_register
processor_get_register_names
processor_in_debug_mode
processor_reset
processor_run
processor_set_register
processor_step
processor_stop
sld_access_dr
sld_access_ir

by typing help

真是巧合，这和riple开发的Avalon-MM总线上的vjtag master总线调试工具太 像了，都是通过Virtual JTAG来提供Avalon-MM的调试功能。除了基本的总线调试功能，“系统控制台”还提供Nios II处理器调试功能和一些常见的嵌入式调试工具。总线调试功能是这个控制台的最大亮点。

System Console User Guide
Design Files for System Console