以前遇到过几次类似问题，只知道关闭一下就可以通过，但是没搞清原理。在Altera的一篇文档里找到了答案：

In the Settings dialog box, under the Compilation Process Settings section, select Incremental Compilation. Set the Incremental Compilation option to Off.
By turning off the Incremental Compilation option, pre-synthesis signals can be added to the SignalTap II ELA in the later sections. Pre-synthesis signals exist after design elaboration, but before any synthesis optimizations are done. This set of signals should reflect your register transfer level (RTL) signals.

背景资料：Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems