FPGA技术实践文章汇总
0赞实践性的：可以直接指导实践的，可以改进工作方法的。
Mon Apr 12 2010 17:30:20 GMT+0800 (China Standard Time)DDR3 memory interface controller IP speeds data processing applications
Thu Mar 18 2010 10:12:23 GMT+0800 (China Standard Time)Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs
Thu Feb 25 2010 14:08:37 GMT+0800 (China Standard Time)Partitioning an ASIC design into multiple FPGAs
Thu Feb 25 2010 14:05:11 GMT+0800 (China Standard Time)Leveraging FPGA and CPLD digital logic to implement analog to digital converters
Sun Feb 21 2010 16:24:02 GMT+0800 (CST)Chip synthesis: A new approach to RTL implementation
Sun Feb 21 2010 16:08:28 GMT+0800 (CST)Reusable VHDL IP in the real world
Tue Feb 16 2010 07:53:40 GMT+0800 (CST)Partitioning an ASIC Design into Multiple FPGAs
Thu Mar 18 2010 10:14:09 GMT+0800 (China Standard Time)Oooof! My FPGA's Not Working: Problems with *Synthesis Gotchas*
Thu Feb 25 2010 14:02:47 GMT+0800 (China Standard Time)Eeeeek! My FPGA's not working: Problems with the *IP*
Wed Feb 03 2010 18:41:13 GMT-0800 (Pacific Standard Time)Arrgghh! My FPGA's not working: Problems with the RTL
Tue Jan 19 2010 21:10:17 GMT-0800 (Pacific Standard Time)PRODUCT HOW-TO: Automating the FPGA Design Debug Process
Sun Jan 17 2010 21:23:02 GMT-0800 (Pacific Standard Time)Using an FPGA to tame the power beast in consumer handheld MPUs
Fri Jan 08 2010 01:46:37 GMT-0800 (Pacific Standard Time)Power Supply Design Considerations for Modern FPGAs
Mon Dec 28 2009 00:26:51 GMT-0800 (Pacific Standard Time)PRODUCT HOW-TO: Prototyping ASICs using FPGAs
Sun Dec 27 2009 18:54:43 GMT-0800 (Pacific Standard Time)Using yesterday's methodologies to design today's multi-FPGA systems is a recipe for disaster
Mon Nov 16 2009 21:43:10 GMT-0800 (Pacific Standard Time)Free JTAG tools provide new approach to board debugging
Mon Nov 16 2009 21:34:58 GMT-0800 (Pacific Standard Time)Boundary scan and JTAG emulation combine for advanced structural test and diagnostics
Tue Nov 03 2009 21:49:44 GMT-0800 (Pacific Standard Time)I/O Design Flexibility with the FPGA Mezzanine Card
Sun Oct 18 2009 21:57:46 GMT-0700 (Pacific Daylight Time)Lattice, Epson Toyocom offer differential reference clock solution
Thu Oct 08 2009 23:33:52 GMT-0700 (Pacific Daylight Time)Designing an accessible board
Thu Oct 08 2009 11:19:22 GMT+0800Building a standard micro architecture
Thu Oct 08 2009 11:17:43 GMT+0800FPGA Device Reliability and the Sunspot Cycle
Thu Oct 08 2009 11:16:07 GMT+0800A technique for multi-line addressing in OLED displays
Thu Oct 08 2009 11:14:47 GMT+0800Clock sources with integrated power supply noise rejection simplify power supply design in FPGA-based systems
Thu Oct 01 2009 07:27:58 GMT+0800Using complex triggers in an FPGA-based RTL debugger
Mon Sep 28 2009 22:26:08 GMT-0700 (Pacific Daylight Time)Back to the basics: Doing Hardware Counter/Timer design using High School Science
Thu Sep 24 2009 20:16:38 GMT-0700 (Pacific Daylight Time)PRODUCT HOW-TO - Building high-speed FPGA memory interfaces
Sun Sep 20 2009 21:58:59 GMT-0700 (Pacific Daylight Time)JTAG test routines harness device functionality
Sun Sep 20 2009 21:52:36 GMT-0700 (Pacific Daylight Time)Control issues: How FPGAs can address MCUs' general-purpose I/O scaling wall
Wed Sep 09 2009 19:25:46 GMT-0700 (Pacific Daylight Time)Rethinking ReuseFPGA reuse is the same as PCB reuse.
Wed Aug 12 2009 22:28:53 GMT-0700 (Pacific Daylight Time)A New Approach to FPGA Testing and Validation for Today's Market
Wed Aug 12 2009 22:18:12 GMT-0700 (Pacific Daylight Time)Design considerations when using programmable integer-N PLL ICs
Tue Jun 30 2009 22:06:33 GMT-0700 (Pacific Daylight Time)Rapid debug of serial buses in FPGAs
Mon Jun 01 2009 02:36:54 GMT-0700 (Pacific Daylight Time)Programmable clock management increases source synchronous throughput
Thu Apr 23 2009 22:15:34 GMT-0700 (Pacific Daylight Time)Top 10 tips to minimize power consumption when designing with FPGAs
Tue Apr 14 2009 13:01:56 GMT+0800 (China Standard Time)Using an interface wrapper module to simplify implementing PCIe on FPGAs
Wed Mar 11 2009 22:54:28 PDTHow to detect solder joint faults in operating FPGAs in real time
Wed Mar 11 2009 22:54:06 PDTHow to reduce power consumption in CPLD designs with power supply cycling
Sun Mar 1 2009 22:05:44 UTC+0800How to control analog output from a CPLD using a pulse width modulator
Wed Feb 4 2009 09:31:35 UTC+0800Xilinx FPGA introductions hint at new realities1. One (trend) is the emphasis on density rather than performance. In moving to the new families Xilinx has slightly altered their logic-cell arrangement so that a logic slice comprises four six-input look-up tables (LUTs) and eight flipflops. This compares to four LUTs and four flops in the previous generation. 2. Another noteworthy point is the growing importance of high-speed serial transceiver performance. But the LXT also adds—unusually for a low-priced FPGA family—high-speed serial resources: up to eight low-power 3.2 Gbit/s transceivers, four hard-wired memory controllers, and one PCI-Express endpoint block. 3. A third interesting observation is the fragmentation of Xilinx's foundry strategy at the new node. Xilinx Director of Product Marketing Brent Przybus explained that the company chose to split production of the two families between UMC and Samsung... for both time-to-market and capacity reasons. 4. Finally, there is the question of power. But FPGAs still lag far behind ASICs and ASSPs in other means of power management. Voltage islands, dynamic power gating, dynamic voltage-frequency scaling, and threshold-voltage manipulation are still not available in the new Xilinx family. For that matter, of these techniques only programmable threshold-voltage control is available from Altera, and none of the techniques is supported by Xilinx. 5. Xilinx President and CEO Moshe Gavrielov sees many potential new users coming into the FPGA world, not from the ranks of experienced FPGA designers or even ASIC designers, but from the realm of software and systems engineering. In his vision, the FPGA becomes nearly a slate on which systems designers can write a systems-level design, without concerning themselves with the details of implementation. It is a bold, unifying vision that must contend carefully with the reality of the need for fine-grained control over the implementation at some points in many designs.
Tue Jan 20 2009 15:16:44 UTC+0800Using yesterday's methodologies to design today's multi-FPGA systems is a recipe for disaster
Tue Jan 20 2009 15:15:55 UTC+0800Tips and Tricks: Using FPGAs in reliable automotive system design
Tue Jan 20 2009 15:15:12 UTC+0800PRODUCT HOW-TO: Taking the delay out of your multicore design's intra-chip interconnections
Tue Jan 20 2009 14:43:39 UTC+0800Backplane tutorial: RapidIO, PCIe and Ethernet
Tue Jan 20 2009 14:43:16 UTC+0800How to transform video SerDes from a nightmare to a dream
Tue Jan 20 2009 14:41:11 UTC+0800Free Spice software exploits multicore processors
Thu Dec 4 2008 18:19:04 UTC+0800Video processing pipeline designAs in a RISC processor, a key goal for the video pipeline designer is to balance the stages.
Wed Dec 3 2008 18:06:32 UTC+0800High-Performance SerDes Module with Easy FPGA Interface and Cable Detect
Sun Nov 30 2008 09:30:22 UTC+0800How to improve FPGA-based ASIC prototyping with SystemVerilog
Sun Nov 30 2008 09:28:43 UTC+0800Programmable logic use in handsets--The basics
Wed Sep 17 2008 22:29:34 UTC+0800Reducing Power Consumption in a Fiber Channel Switch
Wed Sep 17 2008 22:28:01 UTC+0800Product How-To: Building a configurable embedded processor - From Impulse C to FPGA
Fri Aug 29 2008 12:40:57 UTC+0800Bridging options enable FPGA-based configurable computing
Thu Aug 28 2008 12:39:21 UTC+0800Verilog versus VHDL (which is best?)
Thu Aug 28 2008 12:38:56 UTC+0800How to give crime-fighters a flexible, high-performance edge with programmable logic
Tue Aug 26 2008 20:32:31 UTC+0800Flexible I/O structure allows MCUs to have 'soft' I/O functions
Tue Aug 26 2008 20:31:35 UTC+0800How to use CPLDs to manage average power consumption in portable applications
Tue Aug 26 2008 20:28:23 UTC+0800How to reduce power using I/O gating (CPLDs) versus sleep modes (FPGAs)
Tue Aug 26 2008 20:21:19 UTC+0800Algorithmic synthesis improves designers' efficiency
Tue Aug 26 2008 20:19:49 UTC+0800Using FPGAs to improve your wireless subsystem's performance
Mon Aug 25 2008 22:19:46 UTC+0800Tech Tutorial: Microcontroller design in FPGAs
Tue Aug 12 2008 06:50:24 UTC+0800How to interface FPGAs to microcontrollers随着FPGA的应用日益广泛，这篇文章介绍的内容已经成为FPGA设 计者的一项基本功了。
Sun Jun 29 2008 21:15:59 UTC+0800Single Flow for Interconnecting IP
Sun Jun 29 2008 21:16:40 UTC+0800Timing-driven Simulink FPGA synthesis
Sun Jun 29 2008 21:22:42 UTC+0800Got the BGA Blues?
Sat Jul 12 2008 16:54:50 UTC+0800Tip of the Week---Simple power supply for FPGAs
Thu Jul 10 2008 21:20:56 UTC+0800How to simplify power design development and evaluation for FPGA-based systems
PCB prototypes add value in the design process
Swapping bits improves performance of FPGA-PWM counters
How to enhance signal integrity in high density FPGA based designs
一篇关于如何测试高密度引脚FPGA之间电路连通性的文章。
FPGA的可编程特性使得这样的测试成为可能，FPGA与CPU连接电路的连通性恐怕就不这么好测试。
Digital Signal Processing Tricks - Frequency Translation without multiplication
FPGAs for motor control applications
在LP做研究生课题时，用到了dsp56f805数字信号控制器，这款芯片一个主要应用领域就是电机控制，此外还有语音信号处理。片上的一个外设就是 quadrature encoder，当时没看懂。在这篇文章里就介绍了quadrature encoder的应用。
Maximizing Performance and Reliability of FSMs with Precision Synthesis
先放在这里，抽空读一下，把要点摘抄出来。
CVS Version Management in HDL Designer Series
CVS是工程开发必不可少的工具，我在工作中一直使用。曾经用Tcl开发过几个自动上传下载并编译执行的脚本。
这篇文章介绍了CVS在HDL Designer中的使用，介绍的原则应该可以用于Quartus II工作环境。可以考虑用Tcl开发，然后在Quartus II工作界面上添加自定义的Tcl按钮。
How to prototype your ASIC, SoC, or ASSP using FPGAs
Interfacing FPGAs to DDR3 SDRAM memories
Guidance for Accurately Benchmarking FPGAs。鹬蚌相争，渔人得利。行业巨头 的竞争产生了这样的文档。我可以按照文档的原意使用之，也可以把这篇文档作为在两个厂商之间转换设计的指导文档，也可以用作榨取器件性能的指导文档。
Advantages of the Virtex-5 FPGA 6-Input LUT Architecture。反唇相讥，针锋相对。竞争就是 这样的。通过这篇文档，看到Xilinx器件相对于Altera器件的一大优势是LUT和FF可以分开使用，至少部分是这样的；不像Altera的，单独 用LUT（组合逻辑）或单独用FF（时序逻辑）是很吃亏的。
Plugging hardware-based compression into a server
跨越异步时钟边界传输数据的解决方案骨灰级的前辈写的文章，此人拥有关于FIFO的多个专利。英文原文在此Moving Data across Asynchronous Clock Boundaries；此人的 一篇Gray计数器专利在此Method and system for gray-coding counting，一定要拜读一下。
RTL for Z8000 series CPU?几位骨灰级前辈的跑题讨论。想俺当初毕设就是改写了一款 8051的RTL，当时还真为专利、侵权的问题考虑了很多。
Digital Design with just one clock at one edge这个论坛上 有太多的好东西了，惊喜！
Surprise, surprise: Intermittent power-on reset problem reveals decades-old secret of 8052从一接触51，就发现PIO端口的电路设计很麻烦，尤其像2051这样的mini版。这篇文章给出了一个P0口使用的注意事项，以及误用后的电路表现。
Do engineers really do R&D?预研项目和工程项目确实有很大的差异。制定时间表是立项的重要内容。制定得准确与否， 是立项工作质量的判断标准。“小步快跑”，滚动式开发是个不错的方式。
Mon Jan 7 2008 11:01:54 UTC+0800Get research out of development上一篇文章的系列二
Common mistakes in electronic design电子系统的可靠性设计，在设计PCB时，这些经验是很宝贵的，甚至是难得的。
Tue Dec 18 2007 09:57:20My Gray Code article saves the day!真正的技术实践。不过，解决SSN这一问题的方法可能不只是减少信号的SS（瞬时翻 转），减小信号的驱动电流应该起到同样的作用。
Wed Dec 19 2007 09:10:37Using DCFIFO for Data Transfer between Asynchronous Clock DomainsAltera 第一次给出了完整的跨时钟域数据传输解决方案，够权威。
AN 42: Metastability in Altera Devices
Understanding Clock Domain Crossing IssuesCDC
How to quantify FPGA system-level simultaneous switching noise in a chip/package/PCB designSSN
Tue Jan 8 2008 17:37:51 UTC+0800调节多核处理器硬件适应软件设计方法
硬件和软件设计是两种本质上不同的工作。无论硬件设计语言多么像一个软件，它进行的仍然是硬件设计。硬件语言对结构进行定义，并且设计流程最终要进行结构 的实体化。但是，软件工程师正越来越多地使用C编程技术来设计系统功能；现有的工具支持使用软件或硬件方法来设计系统功能。
软件实现的方法更 偏向于过程导向。它考虑的是“如何去做”而不是“构建什么”的问题，因为从传统观点来看，已经不需要再构建什么了 - 硬件都已经被构建好了。在真正基于软件的设计方法中，关键的功能不是被构建到一种结构中去，而是在一个已经构建好的系统中被结构执行的。灵活性是基于软件 的实现方法的优势：在系统出厂后仍能快捷地对其进行改变。虽然FPGA也能现场编程，但改变软件设计要比构建硬件快捷地多。
由于硬件和软件设 计存在着差异，因此硬件和软件的设计者所考虑的问题是不同的。硬件工程师不可能只通过改变编程语言的语法，就能转变成软件工程师。反之，软件工程师也不可 能因为硬件设计中需要软件的参与，就能转变成硬件工程师。因此，不能轻率地就让软件工程师加入到处理架构的设计中来。
此外，硬件工程师、软件 工程师或项目经理都不会同意将一个基于硬件方法的设计交给一位软件工程师去完成。软件工程师做出关于硬件的决定时所使用的方法，极有可能得到熟悉类似编程 语言的另一位软件工程师的认同。
Thu Jan 17 2008 13:19:33 UTC+0800加速FPGA系统实时调试技术关于泰克的FPGA外部逻辑分析仪原理的好文章！
Fri Jan 25 2008 13:59:54 UTC+0800提高ASIC验证的速度与可视性
Fri Jan 25 2008 14:07:47 UTC+0800基于FPGA的网络处理技术的性能和灵活性分析
Fri Jan 25 2008 15:33:06 UTC+0800利用FPGA平台解决接口的总线速度瓶颈。原理：1. 通过FPGA直接访存提高了数据传输速度；2. 通过增加一片SDRAM减少了单端口RAM访问冲突问题。
Fri Jan 25 2008 16:51:24 UTC+0800提高FPGA设计生产力的工具、技巧和方法指南。本文揭示了可视化技术在时序分析中的重要作用。
Fri Jan 25 2008 18:17:53 UTC+0800How to achieve timing-closure in high-end FPGAs。It is not sufficient for a timing-closure solution – the entire flow, including synthesis – to meet only the required timing; such a solution must also minimize the number of time-consuming synthesis-place-route iterations and provide results that remain stable across multiple physical synthesis runs and during final routing.
Physical Synthesis最初是Synplicity从ASIC设计流程里引入到FPGA流程里的，后来一些FPGA厂商的EDA工具也加入了这一功能。现 在，Synplicity否定了“物理综合”的效果，转用“图形综合”。究其原因，是因为时序收敛不仅仅取决于P&R，还从根本上受到S的影响。 但是对时序收敛来说，S&P&R的过程不是线性的，导致S之后的时序分析结果很不准确，由这个结果反馈回S仍然不能得到准确的结果，只有 经过S&P&R的全流程才能获得准确的结果，所以S&P&R的过程必须经过多次反复，而且还不一定收敛。如果在 S&P集成在一起的步骤之后才进行时序分析，则结果就很准确了，该结果再反馈回S&P进行RTL修改和时序约束，就能够逐步收敛，而且该 过程引入的反复开销很小。对于FPGA来说，“物理综合”是以布局为中心的，更适用于ASIC；而“图形综合”是以布线为中心的，符合FPGA的物理结 构。
Avoiding pitfalls in managing embedded systems projects嵌入式系统工程管理。
利用SmartCompile和赛灵思的设计工具进行设计保存，关于增量编译原理的X文，尤其是 Partition边界对时序影响部分很好。
Comparing IP integration approaches for FPGA implementation，SOPC Builder仍然是最先进的系统互连自动生成工具。
用FPGA构建PCI Express端点器件的最佳平台，其中系统架构和运行效率分析的方法值得借鉴。
基于FPGA的IDE硬盘接口卡的实现，好文章，对我的工作有很大的参考价值。
四大FPGA供应商专家谈FPGA设计诀窍，看看四大门派都有些什么说法。
Sat May 3 2008 15:10:38 UTC+0800Accelerating development and lowering riskthe industry must grow from being centered on IP blocks to offer and use IP subsystems.
Sat May 3 2008 20:56:52 UTC+0800What floorplan information is needed for synthesisModeling interconnect delay during synthesis has always presented a "chicken-and-egg" problem.
Wed Jun 11 2008 21:56:37 UTC+0800WP335 - Creative Uses of Block RAM它山之石可以攻玉，关于双端口 RAM巧妙应用的X文。
Wed Jun 11 2008 22:18:01 UTC+0800WP272 - Get Smart AboutReset: Think Local, Not Global关于要不要复位的X文。
Wed Jun 11 2008 22:05:33 UTC+0800DPA Circuitry and rx_dpa_locked Signal Behavior in Stratix III Devices (Jun 5, 2008)
Wed Jun 11 2008 22:24:32 UTC+0800XAPP215Design Tips for HDL Implementation of Arithmetic Functions
Wed Jun 11 2008 22:26:49 UTC+0800WP275 - Get Your Priorities Right
Sat Jun 14 2008 08:44:22 UTC+0800Preserving The Intent Of Timing Constraints
Sat Jun 14 2008 08:44:50 UTC+0800Static Checks for Power Management at RTL
Sat Jun 14 2008 08:45:45 UTC+0800How to perform meaningful benchmarks on FPGAs from different vendors一石激 起千层浪
Sat Jun 14 2008 08:47:10 UTC+0800ESL Methods for Optimizing a Multi-media Phone Chip
Sat Jun 14 2008 08:48:08 UTC+0800Design Challenges Drive Need for New Routing Architecture
Sat Jun 14 2008 08:50:01 UTC+0800How DFT conquers chip complexity
Sat Jun 14 2008 08:56:11 UTC+0800Doing simple code generation with MS ExcelThis article is very helpful. I can use Excel or Perl or Tcl to generate code for HDL or C from a WiKi page, which is used as an interface document between the Hardware Team and the Firmware Team.
Sat Jun 14 2008 08:58:03 UTC+0800Making design choices between DSP and FPGA
Sat Jun 14 2008 08:59:51 UTC+0800Debugging: Making the move from parallel to high speed serial trace
Wed Jun 18 2008 12:48:43 UTC+0800AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming这篇A文中 提到的用嵌入式MCU更新专用配置芯片的方法可用于系统升级维护中。
Wed Jun 18 2008 13:13:02 UTC+0800http://www.xilinx.com/support/documentation/application_notes/xapp176.pdf配 置是个大问题。
Sun Jun 29 2008 19:58:52 UTC+0800ESL Methods for Optimizing a Multi-media Phone Chip
Sun Jun 29 2008 20:00:04 UTC+0800How to perform meaningful benchmarks on FPGAs from different vendors
