qjfun

fifo的verilog实现

//designfifowithRAMorusingregister//depth=8,width=8;modulesync_fifo(clk,rst,clr,wr_en,rd_en,datain,dataout,fifo_cnt,full,empty);inputclk,rst;inputclr;//syncclearinputwr_en;inputrd_en;input[WIDTH-1'b1:0]datain;output[WIDTH-1'b1:0]dataout;output[WIDTH-
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