// design fifo with RAM or using register // depth = 8, width = 8; module sync_fifo( clk, rst, clr, wr_en, rd_en, datain, dataout, fifo_cnt, full, empty ); input clk, rst; input clr;//sync clear input wr_en; input rd_en; input [ WIDTH-1'b1 : 0 ] datain; output [ WIDTH-1'b1 : 0 ] dataout; output [ WIDTH-1'b1 : 0 ] fifo_cnt; output full; output empty; parameter DEPTH = 4'd8; parameter WIDTH = 4'd8; parameter DEPTH_bit = 2'd3;//depth bit count reg [ WIDTH-1'b1 : 0 ] fifo_men [ DEPTH-1'b1 : 0 ]; reg [ DEPTH_bit-1'b1 : 0 ] wr_addr; reg [ DEPTH_bit-1'b1 : 0 ] rd_addr; wire clk, rst; wire clr; wire wr_en; wire rd_en wire full; wire empty; wire [ DEPTH_bit : 0 ] fifo_cnt; //write always @( posedge clk or posedge rst ) begin if( rst ) begin wr_addr <= 1'b0; end else if( clr ) begin wr_addr <= 1'b0; end else if( wr_en && !full ) begin fifo_men[wr_addr] <= datain; wr_addr <= wr_addr + 1'b1; end end //read always @( posedge clk or posedge rst ) begin if( rst ) begin dataout <= 1'b0; rd_addr <= 1'b0; end else if( clr ) begin dataout <= 1'b0; rd_addr <= 1'b0; end else if( rd_en && !empty ) begin dataout <= fifo_men[rd_addr]; rd_addr <= rd_addr + 1'b1; end end always @( posedge clk or posedge rst ) begin if( rst ) begin fifo_cnt <= 1'b0; end else if( clr ) begin fifo_cnt <= 1'b0; end else if( rd_en && !empty ) begin fifo_cnt <= fifo_cnt - 1'b1; end else if( wr_en && !full ) begin fifo_cnt <= fifo_cnt + 1'b1; end end //full full = fifo_cnt[DEPTH_bit]; //empty empty = ~|fifo_cnt; endmodule

自己写的一个fifo程序，

求指正！