wishbone bus多主机单从机共享

wishbone bus参阅：http://blog.csdn.net/column/details/ce123-wishbone.html

实现两个主设备通过共享wishbone总线访问单个从设备。

module wb_2m_1s ( // WISHBONE common wb_clk_i, wb_rst_i, // WISHBONE MASTER 1 m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o, m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o, m1_wb_err_o, // WISHBONE MASTER 2 m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o, m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o, m2_wb_err_o, // WISHBONE slave 1 s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i, s1_wb_dat_o, ); // WISHBONE common input wb_clk_i, wb_rst_i; // WISHBONE MASTER 1 input [31:0] m1_wb_adr_i, m1_wb_dat_i; input [3:0] m1_wb_sel_i; input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i; output [31:0] m1_wb_dat_o; output m1_wb_ack_o, m1_wb_err_o; // WISHBONE MASTER 2 input [31:0] m2_wb_adr_i, m2_wb_dat_i; input [3:0] m2_wb_sel_i; input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i; output [31:0] m2_wb_dat_o; output m2_wb_ack_o, m2_wb_err_o; // WISHBONE slave 1 input [31:0] s1_wb_dat_i; input s1_wb_ack_i, s1_wb_err_i; output [31:0] s1_wb_adr_o, s1_wb_dat_o; output [3:0] s1_wb_sel_o; output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o; reg m1_in_progress; reg m2_in_progress; reg [31:0] s1_wb_adr_o; reg [3:0] s1_wb_sel_o; reg s1_wb_we_o; reg [31:0] s1_wb_dat_o; reg s1_wb_cyc_o; reg s1_wb_stb_o; reg m1_wb_ack_o; reg [31:0] m1_wb_dat_o; reg m2_wb_ack_o; reg [31:0] m2_wb_dat_o; reg m1_wb_err_o; reg m2_wb_err_o; wire m_wb_access_finished; wire m1_req = m1_wb_cyc_i & m1_wb_stb_i; wire m2_req = m2_wb_cyc_i & m2_wb_stb_i; always @ (posedge wb_clk_i or posedge wb_rst_i) begin if(wb_rst_i) begin m1_in_progress <= 0; m2_in_progress <= 0; s1_wb_adr_o <= 0; s1_wb_sel_o <= 0; s1_wb_we_o <= 0; s1_wb_dat_o <= 0; s1_wb_cyc_o <= 0; s1_wb_stb_o <= 0; end else begin case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case 5'b00_10_0, 5'b00_11_0 : begin m1_in_progress <= 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m s1_wb_adr_o <= m1_wb_adr_i; s1_wb_sel_o <= m1_wb_sel_i; s1_wb_we_o <= m1_wb_we_i; s1_wb_dat_o <= m1_wb_dat_i; s1_wb_cyc_o <= 1'b1; s1_wb_stb_o <= 1'b1; end 5'b00_01_0 : begin m2_in_progress <= 1'b1; // idle: m2 wants access: m2 -> m s1_wb_adr_o <= m2_wb_adr_i; s1_wb_sel_o <= m2_wb_sel_i; s1_wb_we_o <= m2_wb_we_i; s1_wb_dat_o <= m2_wb_dat_i; s1_wb_cyc_o <= 1'b1; s1_wb_stb_o <= 1'b1; end 5'b10_10_1, 5'b10_11_1 : begin m1_in_progress <= 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1. s1_wb_cyc_o <= 1'b0; s1_wb_stb_o <= 1'b0; end 5'b01_01_1, 5'b01_11_1 : begin m2_in_progress <= 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2. s1_wb_cyc_o <= 1'b0; s1_wb_stb_o <= 1'b0; end endcase end end // Generating Ack for master 1 always @ (m1_in_progress or s1_wb_ack_i or s1_wb_dat_i ) begin if(m1_in_progress) begin m1_wb_ack_o <= s1_wb_ack_i; m1_wb_dat_o <= s1_wb_dat_i; end else m1_wb_ack_o <= 0; end // Generating Ack for master 2 always @ (m2_in_progress or s1_wb_ack_i or s1_wb_dat_i) begin if(m2_in_progress) begin m2_wb_ack_o <= s1_wb_ack_i; m2_wb_dat_o <= s1_wb_dat_i; end else m2_wb_ack_o <= 0; end // Generating Err for master 1 always @ (m1_in_progress or s1_wb_err_i or m1_wb_cyc_i or m1_wb_stb_i) begin if(m1_in_progress) m1_wb_err_o <= s1_wb_err_i; else if(m1_wb_cyc_i & m1_wb_stb_i) m1_wb_err_o <= 1'b1; else m1_wb_err_o <= 1'b0; end // Generating Err for master 2 always @ (m2_in_progress or s1_wb_err_i or m2_wb_cyc_i or m2_wb_stb_i) begin if(m2_in_progress) m2_wb_err_o <= s1_wb_err_i; end else if(m2_wb_cyc_i & m2_wb_stb_i) m2_wb_err_o <= 1'b1; else m2_wb_err_o <= 1'b0; end assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o; endmodule

参考opencore上的Ethernet IP core project中eth_cop.v文件