vhdl初学之计数器
用惯了verilog,看vhdl确实复杂多了,尤其是testbench相当麻烦。下面是八位可复位重载计数器vhdl代码极其testbench。libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitycount_8isport(clk,rst_n,load:instd_log
发表于 2012/12/12 20:13:27
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