module gray(input clk, input rst_n, output reg[3:0] gray); reg [3:0]bin; wire [3:0]bnext; wire [3:0]gnext; always @ (posedge clk or negedge rst_n) begin if(!rst_n) begin bin<=0; gray<=0; end else begin bin<=bnext; gray<=gnext; end end assign bnext=bin+1; assign gnext=(bnext>>1)^bnext; endmodule