verilog代码，非常简单：

module add8(a,b,cin,cout,sum); input[3:0]a; input[3:0]b; input cin; output cout; output[3:0]sum; assign {cout,sum}=a+b+cin;//也注释掉这一行，用下面4行也许会好理解一点； // wire [4:0]c_sum; // assign c_sum=a+b+cin; // assign sum=c_sum[3:0]; // assign cout=c_sum[4]; endmodule

下面是相应的VHDL代码，相比繁琐很多，尤其是测试代码。

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity half_add is //从半加器代码改过来的，所以没改名字，实际是八位全加器代码 port( a: in std_logic_vector(3 downto 0); b: in std_logic_vector(3 downto 0); cin : in std_logic; cout : out std_logic; sum : out std_logic_vector(3 downto 0)); end half_add; architecture behavour of half_add is signal c_sum:std_logic_vector(4 downto 0); signal a_int:std_logic_vector(4 downto 0); begin a_int<='0'&a; c_sum<=a_int+b+cin；//必须有一位的位数是和c_sum相同 cout<=c_sum(4); sum<=c_sum(3 downto 0); end behavour; 测试代码： library ieee; use ieee.std_logic_1164.all; entity half_add_tb is end half_add_tb; architecture behaviour of half_add_tb is component half_add port ( a : in std_logic_vector; b : in std_logic_vector; cin : in std_logic; sum : out std_logic_vector; cout : out std_logic); end component; signal a: std_logic_vector(3 downto 0):="0000"; signal b: std_logic_vector(3 downto 0):="0000"; signal cin: std_logic:='0'; signal sum: std_logic_vector(3 downto 0); signal cout: std_logic; begin u1: half_add port map( a =>a, b=>b, cin =>cin, cout =>cout, sum =>sum); process begin wait for 0 ns; a<="1111";b<="1110";cin<='0'; wait for 10 ns; a<="0011";b<="1000";cin<='1'; wait for 10 ns; a<="1011";b<="1111";cin<='0'; wait for 10 ns; a<="1010";b<="0010";cin<='1'; wait for 10 ns; a<="0011";b<="1010";cin<='1'; wait for 10 ns;--这样写后面会循环下去，改成wait则保持。。 end process; end behaviour;