一水寒

vhdl初学之计数器

0
阅读(3538)

用惯了verilog,看vhdl确实复杂多了,尤其是testbench相当麻烦。下面是八位可复位重载计数器vhdl代码极其testbench。

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity count_8 is port ( clk,rst_n,load:in std_logic; load_data:in std_logic_vector(7 downto 0); cnt:out std_logic_vector(7 downto 0) ); end count_8; architecture behav of count_8 is signal cnt_reg :std_logic_vector(7 downto 0); begin process(clk,rst_n) begin if(rst_n='0')then cnt_reg<="00000000"; elsif (clk'event and clk='1')then if (load='1')then cnt_reg(7 downto 0)<=load_data(7 downto 0); else cnt_reg(7 downto 0)<=cnt_reg(7 downto 0)+1; end if; end if; end process; cnt(7 downto 0)<=cnt_reg(7 downto 0); -- cnt(0)<=cnt_reg(0)xor cnt_reg(1); -- cnt(1)<=cnt_reg(1)xor cnt_reg(2); -- cnt(2)<=cnt_reg(2)xor cnt_reg(3); -- cnt(3)<=cnt_reg(3)xor cnt_reg(4); -- cnt(4)<=cnt_reg(4)xor cnt_reg(5); -- cnt(5)<=cnt_reg(5)xor cnt_reg(6); -- cnt(6)<=cnt_reg(6)xor cnt_reg(7); -- cnt(7)<=cnt_reg(7); --还原这几行则是八位gray码计数器 -- end behav; 下面是testbench: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity count_tb is end count_tb; architecture behaviour of count_tb is component count_8 port ( clk,rst_n,load:in std_logic; load_data:in std_logic_vector(7 downto 0); cnt:out std_logic_vector(7 downto 0)); end component; signal clk:std_logic:='0'; signal rst_n:std_logic:='0'; signal load:std_logic:='0'; signal load_data:std_logic_vector(7 downto 0):="00011111"; signal cnt:std_logic_vector(7 downto 0); begin i1:count_8 port map( clk=>clk, rst_n=>rst_n, load=>load, load_data=>load_data, cnt=>cnt); process begin wait for 0 ns; rst_n <= '0'; wait for 40 ns; rst_n <= '1'; wait for 200 ns; load <= '1'; wait for 20 ns; load <= '0'; wait for 100 ns; load <= '1'; wait for 40 ns; load <= '0'; wait; end process; process begin wait for 0 ns; clk <= '0'; wait for 10 ns; clk <= '1'; wait for 10 ns; clk <= '0'; end process; end behaviour;
Baidu
map