library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity LED_SEG7 is
port(
Clk: in STD_LOGIC; --50MHz输入时钟
Rst_n: in STD_LOGIC; --低电平复位信号
Sm_cs_n_out: out STD_LOGIC_VECTOR (1 downto 0); --2位数码管位选信号，低电平有效
Sm_db_out: buffer STD_LOGIC_VECTOR (6 downto 0) --2位数码管断选信号（不包括小数点）
);
end entity LED_SEG7;

--640ms计数产生0-F递增数值
--数码管段选译码显示
architecture SEG_DISPLAY of LED_SEG7 is
signal cnt640ms: STD_LOGIC_VECTOR (24 downto 0); --640ms计数寄存器
signal num: STD_LOGIC_VECTOR (3 downto 0); --每640ms递增数值寄存器
begin
--640ms计数
process(Clk,Rst_n)
begin
if (Rst_n = '0') then --异步复位
cnt640ms <= b"0" & x"000000";
elsif (Clk'event AND Clk = '1') then --时钟上升沿
if (cnt640ms < 10#32000000#) then --320ms计数
cnt640ms <= cnt640ms+1;
else
cnt640ms <= b"0" & x"000000";
end if;
end if;
end process;
--产生每640ms递增的0-F值
process(Clk,Rst_n)
begin
if (Rst_n = '0') then --异步复位
num <= x"0";
elsif (Clk'event AND Clk = '1') then --时钟上升沿
if (cnt640ms = 10#32000000#) then --320ms计数
num <= num+1;
end if;
end if;
end process;
--段选显示值译码
process(Clk,Rst_n)
begin
if (Rst_n = '0') then --异步复位
Sm_db_out <= "0000000";
elsif (Clk'event AND Clk = '1') then --时钟上升沿
case num is
when x"0" => Sm_db_out <= "0111111"; --显示“0”
when x"1" => Sm_db_out <= "0000110"; --显示“1”
when x"2" => Sm_db_out <= "1011011"; --显示“2”
when x"3" => Sm_db_out <= "1001111"; --显示“3”
when x"4" => Sm_db_out <= "1100110"; --显示“4”
when x"5" => Sm_db_out <= "1101101"; --显示“5”
when x"6" => Sm_db_out <= "1111101"; --显示“6”
when x"7" => Sm_db_out <= "0000111"; --显示“7”
when x"8" => Sm_db_out <= "1111111"; --显示“8”
when x"9" => Sm_db_out <= "1101111"; --显示“9”
when x"a" => Sm_db_out <= "1110111"; --显示“A”
when x"b" => Sm_db_out <= "1111100"; --显示“B”
when x"c" => Sm_db_out <= "0111001"; --显示“C”
when x"d" => Sm_db_out <= "1011110"; --显示“D”
when x"e" => Sm_db_out <= "1111001"; --显示“E”
when x"f" => Sm_db_out <= "1110001"; --显示“F”
when others => Sm_db_out <= "0000000";
end case;
end if;
end process;
--位选有效
Sm_cs_n_out <= "00";
end architecture SEG_DISPLAY;