module clk_3_odd (clk,reset,clk_out); //占空比为50％
  input clk, reset;
  output clk_out;
  reg[1:0] state;
  reg clk1;
  parameter s0=2'b00;
                      s1=2'b01;
                      s2=2'b11;
    always @(posedge clk or negedge reset)
      if(!reset)
         state<=s0;
      else
        case(state)
          s0:state<=s1;
          s1:state<=s2;
          s2:state<=s0;
          default:state<=s0;
        endcase       
 always @(negedge clk or negedge reset)
      if(!reset)
         clk1<=1'b0;
      else
         clk1<=state[0];         
  assign clk_out=state[0]&clk1;
endmodule