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IEEE中所有关于Verilog的标准

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发表于 2010/6/12 16:15:25 阅读（2755）
1.
IEEE standard hardware description language based on the Verilog(R) hardware description language

14 Oct. 1996
Summary:The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, ve.....
AbstractPlus| Full Text:PDF(6360 KB)IEEE STD
2.
IEEE Unapproved Draft Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language Superseded by P1800/D6

2005
Summary:SystemVerilog 1800 is a Unified Hardware Design, Specification and Verification language. Verilog 1364-2005 is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the Verilog 1364 .....
AbstractPlus| Full Text:PDF(5019 KB)IEEE STD
3.
Unapproved IEEE Draft Standard for Environmental Assessment of Personal Computer Products, including Personal Computers, Desktop Personal Computers and Personal Computer Monitors Superseded by 1680-2005

2005
Summary:SystemVerilog 1800 is a Unified Hardware Design, Specification and Verification language. Verilog 1364-2005 is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the Verilog 1364 .....
AbstractPlus| Full Text:PDF(757 KB)IEEE STD
4.
IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis

2002 Page(s):0_1 - 100
Summary:Standard syntax and semantics for Verilog HDL-based RTL synthesis are described in this standard......
AbstractPlus| Full Text:PDF(508 KB)IEEE STD
5.
IEEE Standard for Property Specification Language (PSL)

2005 Page(s):0_1 - 143
Digital Object Identifier 10.1109/IEEESTD.2005.97780
Summary:The IEEE Property Specification Language (PSL) is defined in this standard. PSL is a formal notation for specification of electronic system behavior, compatible with multiple electronic system design languages, including IEEE Std 1076 TM(V.....
AbstractPlus| Full Text:PDF(1535 KB)IEEE STD
6.
Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language

2007 Page(s):1 - 668
Summary:This standard provides a set of extensions to the IEEE 1364 TMVerilog hardware description language (HDL) to aid in the creation and verification of abstract architectural level models. It also includes design specification methods, embedde.....
AbstractPlus| Full Text:PDF(7348 KB)IEEE STD
7.
Standard for Property Specification Language (PSL)

2007 Page(s):1 - 156
Digital Object Identifier 10.1109/IEEESTD.2007.4408637
Summary:The IEEE Property Specification Language (PSL) is defined in this standard. PSL is a formal notation for specification of electronic system behavior, compatible with multiple electronic system design languages, including IEEE Std 1076trade (VHDL .....
AbstractPlus| Full Text:PDF(1985 KB)IEEE STD
8.
Verilog register transfer level synthesis

2005 Page(s):1 - 116
Digital Object Identifier 10.1109/IEEESTD.2005.339572
Summary:Not available.....
AbstractPlus| Full Text:PDF(745 KB)IEEE STD
9.
IEEE standard Verilog hardware description language

2001 Page(s):0_1 - 856
Summary:Not available.....
AbstractPlus| Full Text:PDF(3773 KB)IEEE STD
10.
IEEE Unapproved Draft Standard for Verilog? Hardware Description Language (Revision of 1364-1995) Replaced by approved draft

2005
Summary:Not available.....
AbstractPlus| Full Text:PDF(3757 KB)IEEE STD
11.
IEEE Approved Draft Standard for Verilog? Hardware Description Language Superseded by 1364-2005

5
Summary:Not available.....
AbstractPlus| Full Text:PDF(3755 KB)IEEE STD
12.
IEEE Std 1364 -2005 IEEE Standard for Verilog Hardware Description Language

2006 Page(s):0_1 - 560
Summary:Not available.....
AbstractPlus| Full Text:PDF(5970 KB)IEEE STD
13.
Behavioural languages - Part 4: Verilog hardware description language

2004 Page(s):0_1 - 860
Summary:Not available.....
AbstractPlus| Full Text:PDF(4955 KB)IEEE STD

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