CrazyBingo

hyh808问：如何获得完整的SOPC Builder和GNUPro

Bill Yuan答复：如果您购买了我们的开发板，我们随板提供这些软件，包括Quartus II

sdfwx1问：完全版的NIOS需要多少钱？

Horace答复：You can buy the Cyclone-Nios Kit or Stratix-Nios Kit, now has a

special offer ( USD 495 ) upto end of June, 2003 So that you can use Nios. IF

you have further information, please contact me horace@cytecht.com

sjq603问：What diffirence between 3000 and 7000

Edward答复：MAX3000A and MAX7000AE are pin-to-pin compilable,only but

MAX3000A have little 2 or 4 IO than MAX7000AE,these 2 or 4 IO must connect to

GND with MAX3000A.

phdb问：能不能用最简洁的语言谈谈cpld和fpga的区别？谢谢！

eric deng答复：FPGA is gate arry like architecture. It is SRAM base, rich

register, and timing depends on routing path. It is more suitable for more

complex, need register design like counter. CPLD is PAL like architecture. It

is EEPROM base, rich logic and fix timing. It is more suitable for glue logic

like decoder.

strongzhy问：我的设计板上没把象GCLK2这样的管脚接地，在max3000a用MAXPLUS2原理设

计中设计成内部接地可以吗？

Bill Yuan答复：GClk2是全局输入信号管脚，如果不用一定要接地，否则会引入噪声而是

的芯片工作不稳定

bighand问：signaltap通过JTAG口读数据，有没有相关参考资料

Edgar Wong答复：For information about SignalTap II, please refer to

httpwww.altera.comproductssoftwareplddesignverificationsignaltap2sig-index.html

zoro问：可否提供样片？怎么申请样片？

Horace答复：Please let me know your location ( Shanghai, Beijing, ShenZhen

... ) After that, our engineer will contact you. My email address

horace@cytecht.com

myq_2003问：如果在一FPGA中除了做一个NIOS的IP 以外，还有其他逻辑，那么在高层使用

这个NIOSIP就象使用其他的MEGAGFCTIONG 一样呢？

robin答复：Yes!

yangwu问：如何获得评估板

ivan Li答复：You can contact our distributor Cytech.

marktang问：excalibar产品是否有开发板用什么软件进行开发

ivan Li答复：We have Excalibur development board EPXA1 and EPXA10, with tools

of QII, ADS, GNUPRo.

tyoney问：如何获得更多的nios 资料？

Jing Kuo答复：Please check this page, which have all the nios documentations

httpwww.altera.comliteraturelit-nio.html

cuijunwu问：我的tel010-62301681,我想参加altera的定期免费培训

robin答复：You can contact with Cytech Beijing Office to get more imformation

010-82684280 Robin

bighand问：：Altera provide Signaltap to help customer to make debug, through

JTAG port有没有相关资料参考

Edgar Wong答复：For information about SignalTap II, please refer to

httpwww.altera.comproductssoftwareplddesignverificationsignaltap2sig-index.html

wishfree问：在altera的网站上没有找到关于下载电缆的文档啊dsbytemv.pdf

Edward答复：pls go to the website httpwww.altera.comliteraturedsdsbytemv.pdf

zxdony问：What is the difference between FPGA and CPLD

eric deng答复：FPGA is gate arry like architecture. It is SRAM base, register

rich, and its timing depends on the routing path. It is more suitable for

more complex design like counter. For CPLD, it is PAL like architecture. It

is EEPROM, logic righ and the timing is fix. It is more suitable for glue

logic design like decoder.

likuanyu问：请问max3000a系列用什么下在电缆？

ivan Li答复：You can use both ByteblasterMV and ByteblasterII to programme

MAX3000.

sky_hook问：对于初学者来说是不是可以直接学习Quartus2而不用学习MP2，另外Q2支持哪

几种语言

Jing Kuo答复：Yes. We recommend engineers to switch to QuartusII for all

their designs, since QuartusII is much more powerful than Max+PlusII. Quartus

can support, Verilog, VHDL, AHDL, 3rd party netlists, and schematics.

lanhson问：nois是一个纯软件包，装入适当FPGA就可以实现CPU的功能，那么nois可以我

们自己拿过来根据我们的需要做一些修改吗？可以的话，有这方面的工具和一些技术资料

吗？ 请回答，谢谢！

Bill Yuan答复：用我们提供的软件SOPC BUILDER你可以向搭积木一样方便的对NIOS进行配

置，修改。请在我们的网httpwww.altera.com夏在相关的资料，或和代理商联系

luet问：请问专家ALTERA公司能否提供一个应用NIOS开发一个具体的产品的过程(演示板),

让我们对如何运用NIOS有详细的了解

ivan Li答复：Yes, ALtera has provide that NIOS development system, including

Board and tools. You can contact our distributor for that.

hjh123问：max7128与3.3VCPU的IO连接,怎样选取MAX7128的型号

Bill Yuan答复：最适合的是7128AE

joreshe问：how can i get material about nios

Edgar Wong答复：You can refer to this link for information about NIOS

httpwww.altera.comproductsdevicesniosnio-index.html

tgqtc问：请问贵公司有没有与ATF1508AS完全兼容（要求发热低）且价格相当的产品，我

公司用量较大且产品已成型不便立即更改

eric deng答复：Yes. You may consider Altera MAX 3128A device. You may contact

our distributor - Cytech to get more information or go to our website

httpwww.altera.com to look for MAX family.

tangwood问：那我怎么向您索取关于“NOIS”的资料呢

Jing Kuo答复：You can find the info in this page

httpwww.altera.comliteraturelit-nio.html

lnlsn问：最低功耗是多少，最便宜的一种是多少钱？

Edgar Wong答复：If you refer to Cyclone, its standby current is about 10mA.

Regarding price, it is $1.51000LE at 250K volumn.

phdb问：altera公司的这两种器件的安全性如何？其解决方案又如何？如何保护器件的ip

！

Edgar Wong答复：When programming MAX, user can turn on a secuirty option

which prevents programming image from reading out of the device. Regarding

FPGA in general, such as Cyclone, because of its high density and routing

complexity, it is extremely difficult as they do not know exactly the

internal architecture of the device. Even if people can reverse the bit

stream to derive the LUT structure of the design, , to try to reverse it back

to the original gate level logic, not to talk about the RTL or architectural

level, it would be near to impossible. If they are concerned with people just

copying the FPGA content and reproduce the same board, they can put a small

portion of the design into a CPLD.

sdfwx1问：利用NIOS做图象压缩（JPEG）行的通吗？

robin答复：1,Nios in FPGA is Flexibility low cost Scalability SOPC solution.

2,With your specail application,you can use user logic as co-processor and

you can get a high performance and flexibility systme.

sdfwx1问：NIOS能否在7000中使用？

Bill Yuan答复：不能，只能用在FPGA中

lishuanghua问：3064里面的数据可以再读出来吗？

Bill Yuan答复：如果编程的时候加密了，就不能读出来了

fishren问：ALTERA的仿真软件，现在是不是只有MAXPLUSII和Quartus II呢？能否告诉我

目前两个软件的最新版本是多少吗？？

Bill Yuan答复：这两个软件的最新版本maxplus II 10.22和Quartus II 2.2 + SP2 你也

可以使用第三方的仿真软件来仿真如modelsim,vcs等

21IC问：Mazz提问有人说MAXPLUSII编译时如果提示可用资源少于20％，可能会导致逻辑仿

真波形对，而实际运行可能会不稳定,是不是这样？

21IC答复：OK.

sean_wang问：您提到的低成本的解决方案有没有实例？

Edward答复：低成本的解决方案我们有很多,而且现在已经有很多客户已经成功应用在他们

的产品中.

wangjiwen问：max+plus II支持Tsunami吗？

eric deng答复：MAX+PLUS II supports the existing product families like MAX

70003000, FLEX, ACEX etc. For our future products, they will support by

Quartus software.

myq_2003问：什么样的fPGA适合做NIOS，除了飓风

Bill Yuan答复：Apex,ApexII,Flex10K,Flex10E,ACEX1K,Stratix,Mercury,StratixGX

fishren问：请问MAX系列的CPLD在仿真的时候是否最好按照软件自动分配的IO管脚来连线

呢？据说如果不是这样的话，在很多逻辑时钟等地方那个会有问题？

eric deng答复：MAX+PLUS II software will choose the best placement for

design. Base on this placment, you can get most effecient performace. If you

are using manaul pin-locking, it may not be the best placement, so it may

cause the routing problem. So we suggest you let software to do auto pin

assignment to get best performace.

lishuanghua问：在成都有你们的办事结构吗？

Horace答复：Thanks for your enquiry. You can contact Cytech ChengDu office.

The phone number ( 028 ) 86527116, 86527226, 86527336

myq_2003问：冒昧的问：Excalibur device 是贵公司的什么样的产品

Edward答复：Excalibur device是嵌入ARM CPU 的一个系列,提供客户更高的SOPC方案,目

前嵌入的是ARM922T.

canda问：请问maxplus2支持c语言编程吗？如果不，什么支持？是专用c语言吗？有没相关

资料

Bill Yuan答复：不支持C语言，可以支持VHDL，AHDL,Verilog等硬件描述语言

sheepbaa问：NIOS 报价，我在哪里可以找到？

Horace答复：Please let me know your contact information ( Address, PHone

number ), so we can contact you and quote to you soon. My email

horace@cytecht.com

heros问：我可以用jtag口进行测试吗？（比如，我想吧一个输出管脚的信号采集到pc里（

我用的ep20k100e)）

ivan Li答复：Altera provide Signaltap to help customer to make debug, through

JTAG port. You can use signaltap to adopt signal from board into QII to

analyse.

bus问：天津有代理吗？

Horace答复：Please contact Cytech Beijing office ( 010 ) 82684280 for further

details.

strongzhy问：象GCLK2等特殊管脚如不用也如您上面说的操作可以吗？

Bill Yuan答复：gclk2如果没有使用，一定要接地

iamlci问：我已经给你们发了E-MIAL，谢谢你们你们的演讲，希望能收到你们的资料

Horace答复：Yes, we receive, and our people is following your request.

picklezbg问：Nios可以设置成16bits的内核吗？我可以免费得到Demo板的原理图吗？

robin答复：Yes.You can set up a 16-bit data with NIOS for your applicaion.

other side,NIOS is support CC++. About your special problem,you can contact

with your loacal Cytech FAE to get more support.

XUHUI1106问：请问MAX3000和MAX7000有什么区别？

eric deng答复：Both 7000AE & 3000A are 3.3 V devices their density range are

from 32 MC to 512 MC. 7000AE is our high performace family. It offers more IO

(compare with same pacakge) and offers more package choices. 3000A is low

cost solution which offers very attractive pricing.

hjh123问：nios 价格如何,以前我用过类似的SOC,但由于价格高而不能产品化

Horace答复：Please let me know your contact information, then we will contact

you for further detail discussion. My email horace@cytecht.com

jxlee问：请问byteblaster 并口 和 byteblaster MV 并口下载电缆的区别？是否通用？

Bill Yuan答复：byteblasterMV 可以支持3.3v的器件下载和编程，byteblaster只支持5v

器件 byteblasterMV可以替代byteblaster 5v

wxzhuhua问：价格低于1美元 那是什么芯片 有多少引脚

ivan Li答复：MAX3032A with smallest package.

sdfwx1问：用NOIS做一个具有网络接口的中断是否可以？

Edward答复：Yes,NIOS can do it,maybe you should have DMA for the IRQ function

to control the Ethernet interface.

mig29问：国内有用NIOS 的吗？

Horace答复：Yes, local China customers are using Nios on different

applications.

hyh808问：max7000s 的pin支持inout吗？

Edward答复：支持,只要不是专用的输入腿.

marktang问：How can I get SOPC builder Freely Is it embeded in quartus ii now

ivan Li答复：SOPC builder has already embeded in QII from Version 2.X. You

can use it if you have install the QII.

lishuanghua问：3000和7000比较除了电压不同外还有什么不同？

eric deng答复：For 7000S is 5V device; 7000AE is 3.3V device; 7000B is 2.5V

device and 3000A is 3.3V device. 7000AE is our high performace family which

has more IO (compare with same package) and has more package choices. 3000A

is our low cost solution and its pricing is very attractive. The density for

both 7000AE & 3000A is from 32 MC to 512 MC.

sdfwx1问：nois是一个纯软件包，装入FPGA就可以实现CPU的功能，是这样吗？

Bill Yuan答复：是的，前提是选定的fpga要合适

lanhson问：推荐一些有关nois的开发技术资料？ 可以吗？

robin答复：You can get more document from altera websit. httpwww.altera.com

or you can contact with local cytech FAE to get more support.

myq_2003问：既然飓风是一款好性能低成本的FPGA，那么也其他FPGA比较，他有如此低的

价格，那么他在技术上是否做了写回扣？

ivan Li答复：Cyclone之所以是这么低的价格, 主要是因为我们采用了最先进的工艺和技

术.

hjh123问：广州是否有代理altera代理

Horace答复：Cytech also support GuangZhou customer. Please contact our Cytech

office ( 0755 ) 83867431

myatmel问：程序下载电缆从网上下载的原理图和你们提供的下在电缆完全一样吗？

Bill Yuan答复：如果是从Altera网站上下载的，肯定是一个样

likelives问：请问北京是否还有定期的免费培训

Horace答复：Please let me know your contact information. We will send the

information to you My email horace@cytecht.com

justwait问：nios是不是适用大型的系统设计？那到底多大能体现它的优势？

Bill Yuan答复：NIOS是一个使用非常灵活的软核CPU，可以根据用户的需要进行配置，你

可以将它配置成一个功能非常完备的，性能很好CPU，但是会占用多一点的资源，也可以配

置成一个很小的CPU，占用的逻辑单元最小的大概需要1000个

jerry_zzq问：我因为有事，未能听专家演讲，你们有没有计划刻演讲光盘。

Edgar Wong答复：You can come back to this site later for an archived

presentation.

zhanhuabin问：nois支持verilog hdl语言吗？

ivan Li答复：Nios can be implemented with Verilog HDL language, you just need

to select it during you open SOPC builder.

altera大量技术问题答复(1)

1su2ns3 发表于 2/6/2004 5:40:38 PM EDA 技术 ←返回版面

xiaoweihua问：ByteBlaster II下载电缆可以自己做吗?

ivan Li答复：Yes, Altera has released ByteblasterII schematic on web.

quguangn问：max3000a是在线可编程的吗？需要购买编程器？

Jing Kuo答复：Yes MAX3000A has in-system programmability. You can re-program

the device thru the JTAG port,using ByteBlaster, or using CPU to emmulate the

Byteblaster.

myq_2003问：听说ALTERA很多产品都不支持三态，是这样吗

Bill Yuan答复：我们的可编程器件都支持三态输出

jpangpeng问：MAXPLUSII和Quartus II能免费得到吗？

ivan Li答复：You can go tohttp://www.altera.com/to download QII and MP2

Free version.

hibive问：基于SRAM的FPGA通过JTAG下载使用的次数是不是无限次的？EEPROM的有次数限

制是吗？

Bill Yuan答复：Yes

phdb问：为什么可用资源少于20%后，运行不稳定，我现在设计了一个产品，可用资源少于

10%，请问我能用所选器件吗？需要更换逻辑单元更多的器件吗？

Jing Kuo答复：As long as you can fit the design into the device and your

simulation is correct, you can use the device. Howver, if you find the

performance not stable, it is probably caused by other crutial factors, such

as signal integrity, test holes, asynchronous paths, ground bounce, etc., and

you should get them taken care of first.

hpr951511问：请问：怎么体现低成本呢？

robin答复：You can select low cost altera CPLD or FPGA for your application.

You can contact with local Cytech local FAE to help select detail type device

for your application.

youkely问：我是一个单片机应用都有，对CPLD是一个初学者，想知道在Lattice 和Xilinx

和 Altera 哪一家更适入门及应用，还有就是在语言上和逻辑图上哪一种用的更适合设计

。学哪一种更有前途。

eric deng答复：It needs longer time to discuss your question, we will contact

you regarding your question after the seminar.

jxlee问：器件的供货周期一般多长？谢谢！

Horace答复：Please let me know you contact information with location, so we

can discuss with you and let you know exactly for your requested part. My

email address: horace@cytecht.com

bighand问：：Altera provide Signaltap to help customer to make debug, through

JTAG port。有没有相关参考资料说明

Bill Yuan答复：Yes, you can visit our website to get the document.Thanks

luet问：那么假如我要实现这样的功能:双串口\内带WATCHDOG\2K FLASH RAM\2K ROM\4个

定时器\8个中断源\USB接口.....用NIOS+PFGA都能实现吗?

ivan Li答复：Yes, you can customize the NIOS core as your own configuration,

within SOPC builder. But you need to take care to find a correct device to

fit your requirement, with enough resource.

jpangpeng问：如何免费得到quti2开发包或IDE环境

Bill Yuan答复：你可以去我们的网站下载，地址是：

https://www.altera.com/support/software/download/sof-download_center.html

sdfwx1问：为何不把现有CPU内核潜入FPGA，这样成本和开发都好？

Edward答复：We have another Excalibur device which have ARM922T in it,and it

have gone to the marketing on 2001.

zhouzwei问：在深圳有你们的办事处吗？另外那里可以咨询到更多地介绍和使用帮助。

Horace答复：In Shenzhen, you can contact Cytech ShenZhen office, the phone

number ( 0755 ) 83867431

likuanyu问：max3000a支持3态输出，请问控制线是不是一定要用GOE呢？

Bill Yuan答复：不是一定要用GOE才能做三态控制信号，在资源允许的情况下，其他IO也

可以，你可以先用maxplus II 或Quartus 跑一下

gybbh问：请问Stratix系列的EP1S40在综合的时候是否最好按照软件自动分配的IO管脚来

连线呢？如果不是这样的话，会不会有问题？

Jing Kuo答复：We actually recommend you plan the pcb layout, and make pin

assignments according to your pcb layout first. This would make your layout

easier and QuartusIIs fitter more efficient. However, during planning your

pcb, you should consider the constraints of each of the i/o banks. Please

refer to the I/O standard section and pin-out section from this page:

http://www.altera.com/literature/lit-stx.html

yangwu问：开发板能安装linux 吗？

robin答复：Yes.You can

zheqiao问：turbo 译码Ip core 怎么获取

ivan Li答复：You can access to our web:http://www.altera.com/,and find it

in the IP core list.

hjh123问：刚才专家回复 价格低于1美元的MAX3032A with smallest package,是否有其他

附加条件,如果我公司想购买30片,是否这个价格?

ivan Li答复：You can contact our distributor for the detail price about this,

the price doed depend on the volume.

zhouzwei问：可否再多提供一些低成本解决方案？

Horace答复：Please let me know your contact information, so our engineer can

contact you for further discussion. My email address: horace@cytecht.com

quguangn问：max3000a器件在5v系统中可以使用吗？

eric deng答复：For MAX 3000A, the core voltage must connect 3.3V. For its

I/O, it may connect to 5V device.

mig29问：我没有明白NIOS的DEBUG的方法？

robin答复：1,You can use mysupport in altera websit:

https://mysupport.altera.com/eservice/login.asp and provide your problem.

2,Pls contact with your local cytech FAE to get more support.

xiaoniu3问：我来晚了，希望收到演讲的资料。谢谢了

Horace答复：Please let us know your contact information. Please send your

information to this email address: lisalo@cytecht.com

ningxiuwen问：我已经添写了调查表，我真的能收到你们的光盘资料吗？

Edgar Wong答复：Yes. Please make sure that your verify your address to be

correct.

低价转让Altera公司所有的 IP Core (正版)!!!

用ALTERA的IP Core 太容易做设计了!!!

仅ALTERA就有47个!!!

任何人都可以去http://www.altera.com/products/ip/ipm-index.html下载,填个表格就

行了!(全功能,如编译、仿真等，但如果没有正版狗和LICENSE文件,Quartus II 就不能生

成下载文件*.pof和*.sof,用于购买前评估).

altera大量技术问题答复(3)

1su2ns3 发表于 2/6/2004 5:45:03 PM EDA 技术 ←返回版面

iamlci问：杭州的代理点在正常情况下什么时候能够开始提供服务？谢谢

Horace答复：We will let you know, please let me know your email address, so

we can inform you once setup.

平凡的人问：我现在用3064AT100-10里面是用原理图方式集成了74系列的几个器件但是有

些问题,请问需要注意什么,它的引脚有什么特殊的地方.

Edward答复：EPLD和74系列会有区别,用EPLD不推荐用词74系列复制原来的设计,这样基本

上肯定有异步延时的问题.你的问题MAX3064设计应该不复杂,请联系骏龙科技工程师解决.

yfnint123问：cpld输入输出之间可以做到时延固定，而fpga却因设计不同而不同，对吗？

eric deng答复：Yes. Because CPLD is PAL architecture, the timing is fix. For

FPGA, the timing is depending the routing, so the timing is vary.

luet问：请问:如果用NIOS配置完FPGA/CPLD后,如果要实现具体的功能,如何进行编程?我以

前主要用C和汇编在KEIL下编程调试,如果用NIOS应该怎么做?

robin答复：luet:请问:如果用NIOS配置完FPGA/CPLD后,如果要实现具体的功能,如何进行

编程?我以前主要肅和汇编在KEIL下编程调试,如果用NIOS应该怎么做? You can use

GNUPro compile,link,and debug your software.other side,you can use serial

port or JTAG to degug your software or download your software image to flash.

tgqtc问：请问CPLD的发热问题怎样解决，我用的是ATF1508AS

Bill Yuan答复：ATF1508AS不是我公司的芯片

zzengx问：请问excalibur器件速度能否达到125Mbps?

ivan Li答复：Yes, Excalibur device can run at about 200Mbps.

wxqtjcom问：what difference among EPLD, PLD, PLA and FPGA ?

eric deng答复：PLD & PLA is the general term for all programmble deivce. PLD

is including FPGA & CPLD. For FPGA, is Gate Arry like architecture. It is

SRAM base, so you need to have a ROM to contain your data. Also its timing

depends on the rounting path. However, it has rich register, so it is more

suitale for more complex design like counter. For CPLD (EPLE), it is PAL like

architecture with fix timing. And it is EEPROM base device with rich logic.

It is more suitable for glue logic design like decoder.

lishuanghua问：3064 44脚io口少了点，100脚又太大了，没有比较适中的封装？

ivan Li答复：Altera will have plan to release 84 pins package for this.

xddjd问：怎么样解决组合电路中的毛刺问题？ 我看了一篇ALTERA的文章，说一些顺序变

化的码，可考虑格雷码，但是用格雷码之后，用MP2仿真还是有毛刺！

Bill Yuan答复：导致毛刺的原因有很多，简单的改变计数的编码不一定可以解决问题，最

主要的是要设计同步，毛刺基本不会影响同步的设计

muhtar0416问：能否提供一些资料

Horace答复：Please let me know your contact information. My email address:

horace@cytecht.com

玉玟问：有没有可以免费的Nios资料？

Edgar Wong答复：Yes. You can find free information of NIOS with this link:

http://www.altera.com/literature/lit-nio.html

zheqiao问：modsim仿真需要在Q2软件上进行编译连接吗

Edward答复：Modsim can do function simulator without the interface of

QuartusII output,and if you will do the time simulator,you must compile the

design by QuartusII,then you you can use the *.sdo file to simulate in

Modsim.

scanli问：怎样得到qutaru ii full 版？

ivan Li答复：You can both request for our web and contact our distributor to

get the QII full license.

wxqtjcom问：我现在也想学习PLD，是不是告诉你们联系地址就可以得到辅导资料啊？

Horace答复：Please send us your contact information ( company, address,

email, phone number ) My email address: horace@cytecht.com

hobodom问：请问专家，stratix系列芯片是否在各个代理处都有销售，骏龙有的卖么？需

要多少银子？多长时间可以拿货？

Horace答复：Yes, Cytech can sell Stratix Please let me know your contact

information ( email, address, phone ) My email: horace@cytecht.com

strongzhy问：请问max3000a系列未用到的管脚是否可以开路

Jing Kuo答复：Yes. You can reserve the unused i/o pins as tri-stated input.

But you first have to include the empty pins in your design, and give pin

assignments to them. If you have a lot of such pins, say, 100. You can create

an 100-to-1 mux, compile the design, and back-annotate the pins. Then remove

the mux logic and output, but keep the input pins in the design. Also

remember to remove the mux output from pin assignments. This way the 100 pins

would be reserved as tri-state inputs

tinazhu问：请问关于设计的功耗问题，不知道在仿真中的精确度是多少？

Edgar Wong答复：Dynamic power consumption of a device highly depends on the

toggling frequency and data pattern of its inputs. Therefore, if the

simluation stimulus are closer to the actual operation condition of the

device, the accuracy of power consumption estimation will increase.

holly问：cyclone是否能支持ｃ语言的开发

robin答复：In fact,you can use C/C++ in Nios cpu.

玉玟问：Noice要有什么语言编程？

Bill Yuan答复：C 或 C++

sheepbaa问：建议在杭州设置代理点。

Horace答复：Yes, Cytech is planning and will setup soon.

xiaoweihua问：NIOS不能用汇编来开发吗?

ivan Li答复：Nios can be developed with assembly language, and altera provide

the assembly language description for customers.

zhouzhengf问：maxplusii对vhdl语言的支持有限，quartus在这方面有否加强？

Edward答复：QuartusII support better with VHDL,but we suggest the customer

use the 3rd EDA tools to synthesis the VHDL or Verilog,then use our QuartusII

to compile.

xch2000_1980问：下载时总是提示unrecognised device or socket is empty,请问是什么

原因（用ByteblasterMV，WINXP系统，EPM7512AEQC208-10）

Edgar Wong答复：MAX+PLUS II Help describes several causes for this error

message. The following are three additional possibilities that are not listed

in MAX+PLUS II Help: You may receive this error if you attempt to program a

device when the Altera download cable is not powered. These cables receive

power from the printed circuit board (PCB). Ensure that the PCB is powered

properly and that the Altera download cable is securely connected to the PCB.

This error may also appear if you are attempting to program or configure one

device when you actually have more than one device in a Joint Test Action

Group (JTAG) chain. Click on Select Programming File (JTAG menu ->

Multi-Device JTAG Setup). Choose your file and click OK. Click on Detect JTAG

Chain Info.

hbrave问：MAX3000大概什么在国内上市

ivan Li答复：Max3000 has already been used by China customers for more than 1

year.

shirial问：用nios开发一个具有89c51单片机功能的芯片需要多大容量的fpga芯片，价位

大概多少？

robin答复：用nios开发一个具有89c51单片机功能的芯片需要多大容量的fpga芯片，价位

大概多少？ You can choose 16-bit data with NIOS in your application.(need

about 1600LE).How about your other Logic need except NIOS cpu?

lishuanghua问：艾睿公司也是你们的代理吗？我觉得他们还要好一些

Horace答复：Please let me know your contact point and case. My email address:

horace@cytecht.com

marktang问：有没有带AD/DA的FPGA?

Bill Yuan答复：目前还没有，需要外接

qanmingx问：在西安有没有经销商？

Horace答复：You can contact Cytech Xian office Phone number ( 029 ) 8378918

or 8378919

strongzhy问：请问MAX3000a系列没用到的管脚是否可以开路

Bill Yuan答复：如果定义为输出或没有定义，可以开路如果是输入脚并且没有使用，需要

接地

zhouzhengf问：sopc builder是自动生成引导程序引导硬件的自检和软件的运行？

ivan Li答复：SOPC builder can generate Hardware and software automatically,

you can follow SOPC builder wizard step by step.

mikezhang问：我看到专家推荐的CPLD是MAX3000A，这个不是很老了吗？容量确实很小呀！

为什么不讨论讨论用的更多的Max7000呢？我用的就是Max7000的

eric deng答复：Both MAX 7000AE & MAX 3000A are the popular families for CPLD.

The density for MAX 7000AE & MAX 3000A are the same - from 32 MC to 512 MC.

For our 7000AE, it is our high performace family which has more I/O (compare

with same package) & more package chioces. For MAX 3000A, it is low cost

soultion and its pricing is very attractive.

myq_2003问：quartus都有那些版本，如何得到？是free的吗

Bill Yuan答复：Quartus II Full Edition Quartus II Web Edition--Free,can

download from altera website

明空问：那些器件可以不用串接电阻即可支持5v pci

Edward答复：The device which have 5V tolerate I/O can support 5V

PCI,MAX7000AE,MAX7000S,FLEX,APEX20K.Pls check the datasheet of the device

with Mulit-Voltage I/O function.

ehuang999问：请问演讲资料如何下载？

Horace答复：Please send me your contact point. My email address:

horace@cytecht.com

lbkong2002问：altera公司为何不在武汉进行每月的技术培训

Horace答复：Please send your company name, address, and phone. Cytechwill

follow up this Altera Training.

zoro问：刚才听讲作的实例中提到建立一个UART的速率是。。。，可否建立一个速率可调

的UART？可以自动设置吗？

robin答复：You can chang parameter of UART in Nios application for you

special need.

strongzhy问：max3000a不用的管脚怎么处理？

ivan Li答复：You can assign unused IO pins as input, and connect it to

ground. That could reduce the risk of being influenced.

lishuanghua问：nios有c语言吗？

Bill Yuan答复：yes

scanli问：qutaru ii 正式版和网络版有何不同？

Edgar Wong答复：If you refer to Quartus II...Full version supports all

devices, while web edition supports selected devices. Please refer to this

link about devices supported by web edition:

http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.h

tml?xy=ds2_quawe

lyghj问：FPGA内部的RAM速度最快是多少？

ivan Li答复：Embeded memory of different altera device families has different

performance. For example, Stratix internal memory can runnning at about

300MHz.

xiaoweihua问：nios有没有嵌入式操作系统的支持?

Bill Yuan答复：目前有以下一些嵌入式操作系统可以支持NIOS Nucleus Plus

µClinux µC/OS-II KROS visualSTATE

曹军义问：colony 和 flex家族最大的区别是什么.在Flex的逻辑可以移植到colony上吗?

robin答复：Cyclone is newest Altera FPGA. If you use Cyclone,you will get a

high performance and low cost. You can easy migrate your design to Cyclone.

If you have special problem about it,you can contact Local Cytech FAE to help

make clear your prolbem.

hjh123问：Max 3000A& Max7000的区别,指性能和价格或应用方面

eric deng答复：MAX 7000AE is our high performace solution & MAX 3000A is our

low cost solution. MAX 7000AE offers more I/O (compare with same package) &

more package selection. However, the pricing of MAX 3000A is very attractive.

玉玟问：VHDL和Verilog这两种语言，那一种更实用一些？

Edward答复：VHDL和VERILOG现在都比较通用,基本上VERILOG比VHDL语句更简洁一些,所以V

HDL也就更易懂.我们ALTERA支持多种语言嵌套使用.

sunxj问：How to get your free trial-version of Quartus II CD?

eric deng答复：You can get free Quartus II CD from our distributor - Cytech.

Or you can download from our website http;//www.altera.com/.

xddjd问：ALTERA很不注重小公司吗？用骏龙这种代理商是不是太烂了！！！

Horace答复：Please let me know your contact point, we will help you to follow

平凡的人问：有什么仿真方式吗?有类似仿真器的仿真工具吗?

Jing Kuo答复：There are a lot of Simulation tools in the market now, such as

ModelSim, VCS, VSS, Verilog-XL, Active-HDL etc. Altera also provide embedded

logic analyser, SignalTapII, for hard debug.

xddjd问：有一次从骏龙买MAX7128，过了好久还把我们的货给别人了？最后剩一片问我们

要RMB815，是不是太黑暗了？

Horace答复：Please let me know your contact point, we will help you to follow

tiger_ning问：请问专家:maxplus 是不是没有手布线功能？

ivan Li答复：MP2 will not support place Routing of interconnect manually, but

you can use place LE location to control Routing.

myq_2003问：nois用什么语言来写程序

Bill Yuan答复：使用C或C++语言

iamlci问：在杭州可有经销商？

Horace答复：Please contact Cytech Shanghai office. The phone number ( 021 )

64401373

iapnju问：好像也有flash工艺的cpld

eric deng答复：Yes. There is flash base CPLD. But EEPROM base is more popular

in the market, and we did not see any advantage for flash base CPLD.

luet问：用NIOS配置完PFGA/CPLD后是不是已经可以作为CPU使用,比如代替单片机?

Jing Kuo答复：NIOS can be designed into FPGA, but not CPLD yet. And yes it

can be used as a CPU. Please check the details in this page to know which

types of cpu it can replace.

beatxym问：cyclone需要的下载电缆是怎样的？与flex系列的是否可以通用？

Bill Yuan答复：可以使用通用的byteblasterMV来下载Cyclone器件，但是只有用ByteBlas

ter II才能编程用于配置Cyclone的配置芯片EPCS1,EPCS4.

tanghe2001问：请问你们在深圳有代理公司吗？能提供技术支持吗？

Edgar Wong答复：Yes, we have distributor in Shenzhen. You can find the

distributor contact information with this link:

http://www.altera.com/corporate/contact/sales/intl_distis/con-int_distis.html

lishuanghua问：nios有c语言吗？

ivan Li答复：Nios can support C language . And altera will support

development tools.

myq_2003问：如何得到sopc软件

Edgar Wong答复：One of the quickest way is to contact your nearest Altera

distributor for information of the software. You can find the distributor

contact information with this link:

http://www.altera.com/corporate/contact/sales/intl_distis/con-int_distis.html

lizhen7799问：nios是怎么类型的CPU，它是由ALTERA开发的吗！！我们可不可以了解的它

的结构及工作原理啊

ivan Li答复：Nios is a soft core designed by Altera, you can find more detail

information in our web:http://www.altera.com/.

sunxj问：How to get your CD containing free trial version of the software

overseas?

Horace答复：You can download the trial version on Altera web, or you can give

me your contact point ( Address, phone number ), so we can send the trial

software to you also. My email: horace@cytecht.com

曹军义问：请问应用Flex器件可以进行NIOS开发吗？

Edward答复：不可以,我推荐你用CYCLONE系列开发NIOS.

xiaoweihua问：nios到底是什么核?是51的?还是ARM?还是另外别的类型?它的汇编指令跟谁

比较接近?

robin答复：Nios is a RISC Architecture CPU.

zcl1229问：MAX PLUS—ii怎么没有介绍呢！我一直在用这种软件，应该说也能完成10k芯

片设计

ivan Li答复：Both MP2 and QII can be used to implement Flex10K device, but

Altera recommend customer to use QII to make design, because QII will support

all the altera device and will have update version in future.

mazee问：5V DSP信号能直接和3.3V的EP1K30 的IO连接吗？有没有需要注意的地方？

Bill Yuan答复：如果dsp的I/O口符合标准的TTL电平标准，可以直接相连

starlq问：低价的fpga适合用于什么场合？

Horace答复：You can use on different applications, such as communication,

consumer product, industrial product ... so on.

zhzhdao问：Can you tell me the difference between FPGA and CPLD except the

configure?

eric deng答复：CPLD is EEPROM base, PLD like architecture with fix delay

time. It is more suitable for glud logic design like decoder. FPGA is SRAM

base, small base with rich register and the timing is base on the

interconnect rounting. It is more suitable for more complex system design

like counter, pipline.

陶军辉问：我现在正在学习PLD，请问我应该怎么样学习，才能够在最段的时间内掌握。谢

谢！

Edgar Wong答复：One of the quickest way is to contact your nearest Altera

distributor and ask them to provide you some trainings. You can find the

distributor contact information with this link:

http://www.altera.com/corporate/contact/sales/intl_distis/con-int_distis.html

zzengx问：请问我如何在Excalibur 开发板中配置嵌入式linux? 谢谢

robin答复：可以。

altera大量技术问题答复(4)

1su2ns3 发表于 2/6/2004 5:46:58 PM EDA 技术 ←返回版面

guoyingwu问：您好，我想下载并口的电缆线能做多长？我们做过一个大于60公分就不行。

Bill Yuan答复：下载电缆的长度和工作的环境和下载电缆中的244芯片的驱动能力有关，

建议小于50公分，如果需要加长，可以使用并口延长线

玉玟问：审请到的MAX-PLUS的LICENSE为什么用不起来

Horace答复：Please let me know your contact information, and we will arrange

engineer to contact you soon. My email address: horace@cytecht.com

luet问：请问专家:是不是说用nios配置完FPGA后,就可以完全取代单片机的功能了?

robin答复：可以。另外在性能方面，如果配合用户逻辑部分，你可以在不提到cpu频率的

情况下到达很高的系统性能。

XUHUI1106问：请问在开发SOPC时，是不是需要用到的IP都需要另外购买？

Edgar Wong答复：SOPC builder includes free peripherals such as UART,

Timer,SPI, SDRAM controller, Tri-state bridge, AHB bridge, and more. After

you install SOPC builder (come with Quartus II software), free peripherals

and paid peripherals are marked differently.

lllll76问：通过qutaru ii 的实时仿真和实际有多少差别

Bill Yuan答复：我们的仿真软件给出的是最差的工作条件下的器件运行结果，实际的情况

会比仿真的结果好，不会比仿真的结果差

graybear问：Nios以及开发的应用程序所需的内存空间是否可以采用外部存储器，而不用F

PGA的on chip memory

robin答复：可以。你可以根据需要扩充外部地memory。

ningxiuwen问：作为一个初学者，如何得到你们的培训资料？

Horace答复：Please let me know your contact point. My email address:

horace@cytecht.com Then will send you information

iamlci问：请问可否提供样片？我们公司现在正在选型

robin答复：你可以和当地骏龙FAE联系。

hehao问：如果图形输入和语言输入嵌套编程的话，怎么利用synplify或其他第3方工具进

行综合？

Jing Kuo答复：Schematic designs are not transferrable between different

Synthesis tools. So you can only use schematic design in QuartusII or

Max+PlusII. In a mix design methodology, you can use Synplify or other

synthesis tools to compile HDL designs, while compile schematic, HDL,and/or

netlists together in QuartusII or Max+PlusII.

wxp177问：cyclone支持ARM吗？

Edward答复：No,the cyclone can design our NIOS for CPU function,if you want

to use ARM,you can study and use our Excalibur device.you can go to the

website for more information.

http://www.altera.com/products/devices/arm/arm-index.html

wangjiwen问：近期有“NOIS”培训吗？

Horace答复：Yes, we have the Nios Workshop recently. Please send your

information to me ( horace@cytecht.com ) then we will contact you.

graybear问：如果不采用IP核，Nios是否支持外部的接口芯片？例如USB2.0芯片、网口芯

片等。

Edgar Wong答复：Yes. NIOS can easily interface with external logics or custom

interfaces. You can easily specify the interface connection in our SOPC

builder software.

wwqq0121问：can nios work as a simple computer? how fast can it work?

robin答复：是的。你可以在我们的NIOS系统中加入多个外围设备。结合用户逻辑部分，你

定制协处理单元，可以大大加速的系统性能。

iamlci问：MAX3000A在杭州市场的价格是多少？如果邮购呢？

Horace答复：Please contact Cytech Shanghai office. Phone number: ( 021 )

64401373

hehao问：现在FPGA的加密问题越来越受到关注，altera公司在这方面都对fpga做了什么样

的改进？

ivan Li答复：Altera provide FPGA encrypt solution with a white paper, you can

find the that from altera datasheet.

lishuanghua问：Q2好掌握吗？

Bill Yuan答复：如果您有可编程器件设计的基础，还是很容易掌握的

ningxiuwen问：你们在北京有代理公司吗？如何联系？可以免费试用版的quartus II 软件

光盘吗？

Horace答复：You can contact Beijing Cytech Tehnology Ltd The phone number is

( 010 ) - 82684280

wishfree问：Quartus中的并口下载电缆与maxplus的可以通用吗？可以自己制作吗？

Edward答复：通用的,也可以自己制作,可查找文件dsbytemv.pdf

seamas问：How many gates or LE a nios core need?

ivan Li答复：A standard NIOS core need about 1600 LEs, and the minimum nios

core only need about 900LEs.

sheepbaa问：请问我在哪里能得到max plus2的使用说明？

Horace答复：You can download the Maxplus II user guide from Altera web site,

or you can contact Cytech FAE.

yzhonghe问：请问专家，nios最快可以

robin答复：>110MHz fmax Typical（Nios in Stratix or Cyclone）

lizhen7799问：请问设计自己所期望的CPU后怎么与FPGA结合啊！若我用CPU来控制FPGA

ivan Li答复：Altera provide SOPC builder to help you design you CPU system,

which not only generate software source code, such as C head file, but also

generate HDL file for you. SOPC builder could generate good interface between

your CPU and LOGIC design.

qinzh问：5V的TTL器件是否可以直接驱动cyclone系列的芯片？

Bill Yuan答复：需要将Cyclone内部I/O的一个嵌位二极管打开，并在管脚上串接电阻，在

Cyclone上电配置完成之后，才可以接受5V的信号输入

zcl1229问：我只用过max_plus II。其他的软件的索取怎样完成

Horace答复：You can download the Web based software from Altera web site, and

of course you can purchase the full version software from Cytech.

zcl1229问：cpld和fpga的图形输入法的效果不是很理想！是否它只有效应用于简单的设计

Edward答复：图形输入法也可以应用于复杂的设计,我们ALTERA支持多种输入法嵌套输入,

所以我推荐你在顶层用图形,底层用语言的方法更有条理.这方面我们有专门的文档和培训

资料.

zb7401问：嵌入式的arm的调试特点！

robin答复：For your question: Hard Core Advantages Higher Performance Optimal

Die Area / Function Time-to-Market Lots of On-Chip Memory Leverage Large

Existing Code Base

平凡的人问：maxplusII支持3000系列吗?

ivan Li答复：Both MP2 and QII can support Max3000A device.

zheqiao问：请问贵公司的在有没有信道译码领域Ip Core，比如RS Turbo译码

Bill Yuan答复：我们提供很多的信道编码IP Core，包括您提到的RS, 和 Turbo我们都有

dian1231问：epic20,how much?

Horace答复：Please send your contact point to me. My email:

horace@cytecht.com

fiendzzh问：cyclone 锁相环时钟输入是否可以为一正弦波？

ivan Li答复：锁相环时钟输入是数字式的时钟信号,不能接模拟的正弦波信号.

gdsxu问：这套demo的价格是多少

Horace答复：Please let me know which demo kit ???

quyangming问：请问应用MAX PLUS可以进行NIOS开发吗？

Bill Yuan答复：不行，需要Quartus II 软件

luet问：请问陈先生,作为初学者如何才能快速的掌握CPLD/FPGA的开发?

Edward答复：我们ALTERA的软件对于初学者来说很容易学习,另外我们ALTERA和骏龙科技公

司有很多的应用工程师可以提供技术支持.另外你还可以学习一些VHDL的设计知识.

yangwu问：开发板能按linux kernel吗？

robin答复：Yes！

zhouzhengf问：onchip－memory是配置在nios cpu中间还是指配置在所用的fpga中？

Bill Yuan答复：on-chip memory 是指用fpga内部的嵌入存储器块来实现nios软核数据或

程序存储器

ZYB00335问：如何得到你们的书面资料

Horace答复：Please send me your contact information. My email:

horace@cytecht.com

徐涛问：请问有无免费开发环境（试用版也可以），在哪下载？

Bill Yuan答复：您可以去我们的网站http://www.altera.com/下载我们的开发软件maxpl

us II 和Quartus II免费版本，您使用的时候需要在我们的网站

http://www.altera.com/申请一个免费的license即可

qgfice问：在国内 CYlone芯片的价位大致在哪个档次，还有Quartus2.1软件开发工具是不

是具有完整的nois软硬件开发功能 谢谢

Horace答复：The price will be based on your quantity, and Cyclone should be

the lowest price FPGA in the world. For your develop Nios design, in addition

to Quartus II software, you should also have SOPC software, suggest you buy

the Cyclone-Nios Kit which have a special offer till to End of June, 2003.

The price is USD 495 per kit

zhouzhengf问：各位专家是怎么解决fpga中时延不确定对逻辑电路设计的影响的？

ivan Li答复：Altera recommend customer to make synchronal logic in the FPGA,

because you use synchronal logic design, all the application works with

trigger of clock rising edge, which could reduce the different timing skew

when you implement design in different device.

xujin47问：原系统使用MCS-51及Z80处理器，怎样将这些系统转换成“Nios”系统？性能

能否提高？

robin答复：Nios is support C/C++,and you can us GNUPro compile,link,and debug

your nios systme. Nios is RISC architecture CPU.It will run a high better

performance compare with MCS-51 and Z80.

zhouzhengf问：使用nios软核进行产品的批量生产需要申请版权吗？

Bill Yuan答复：如果您只需要将nios使用在Altera的FPGA产品内，不需要另外申请版权，

如果您想将nios移植到ASIC中，则需要另外申请版权

shjjsj问：what is the different between FPGA and CPLD?

Jing Kuo答复：The consensus now is that FPGA is Look-Up-Table based

architecture and CPLD is Product-Term based architecture.

sunhaihuan问：cyclone的明显优势是什么？

ivan Li答复：Cyclone is altera newest device designed with the world advanced

technology, 0.13um, full copper interconnect. The best advantage of cyclone

is low price.

xujin47问：Maxplus2学生版软件对用户有没有限制？能否开发已停产或即将停产的FPGA器

件，例如EPF10K20或EPM7128

Edward答复：对EPF10K20或EPM7128没有限制,而且我们的免费软件还支持全系列的最新MAX

3000A,CYCLONE系列(这次SEMINAR讲到的).

qanmingx问：请问avalon总线及其标准是什么

ivan Li答复：Avalon bus is design by Altera, which is internal bus which

interface to NIOS core. You can find the Avalon bus protocol in the

documentation folder after you install NIOS megafunction.

gxm771208问：how to maximized

Jing Kuo答复：Please let us know what do you want to maximize. Thanks.

fansr问：贵公司提供评估板电路原理图和印刷板图吗，ruhe

robin答复：nios is License & Royalty Free.

fansr问：计划出版Quartus软件相关书籍，公司可赞助吗？要求是什么？

Horace答复：Please send your contact information to us: horace@cytecht.com

lizhen7799问：请问怎么来确定PLD的延时啊

Bill Yuan答复：我们的设计软件Maxplus II 和Quartus II都可以进行时序分析，在分析

的结果中可以清晰地看到每个pin的建立和保持时间，以及时钟信号的fmax，还有管脚倒管

脚地延时信息等，都可以看到

lizhen7799问：nios是什么样的处理器啊

ivan Li答复：Nios is a soft CPU core, 32-bits. Users can customize their own

CPU core with different peripheries as they like. And Nios core can be

implemented in all the altera device if it has enough resource.

sunnychao问：32 bit 的内核的峰值MIPS为多少？

robin答复：nios是一个嵌入在FPGA内部的softcpu，会因为你使用的Altera FPGA的性能有

所不同。在我们的cyclone FPGA器件中，可以到达50DMIPS。

wangyujuan问：开始了吗？

Jing Kuo答复：Yes.

macray问：请问专家，如果因为条件限制，短时间内不能购买贵公司硬件评估产品，能不

能先申请一套软件用于学习？

Edward答复：可以,请联系骏龙公司获取或上http://www.altera.com/下载免费软件,具体

使用可寻求支持.

fyx123问：内部时延和所用时钟有关系吗？在允许频率范围内，是否所用时钟频率越高，

时钟延迟越小？还是固定延迟？

Jing Kuo答复：If I understood your question correctly, you are asking if

clock delay is fixed inside FPGA. The answer is Yes. The delay from a clock

input pin to an internal register is fixed, regardless what frequency it is

running.

quguangn问：需要使用配置信息的flex系列芯片如何加密？可否在线更改配置以实现新的

功能，如何操作？

Bill Yuan答复：flex系列芯片无法加密，不过用户可以在系统中在设计一个EPLD，将一部

分功能用epld来实现，并将此EPLD加密，可以实现整个系统的加密；可以在线更改配置以

实现新的功能，需要预先将所以功能设计好，并将配置文件存储在存储器中，在不断电的

情况下，用控制逻辑或微处理器重新配置新的数据就可以实现新的功能

quguangn问：quartus II 与 max+plus II 有何区别？为何要分成两个开发系统？

ivan Li答复：QII 和MP2最大的区别是对支持的器件的不同.当然在做设计时,QII和MP2的

功能基本上都能完成任务, 只是在界面上有一些不一样. 不过ALTERA主要会向QII 发展,

现在所有的MP2 PROJECT 已经可以在QII中完全兼容.

kevin_li79问：您好!请问CPLD和FPGA的主要区别是什么？

Edward答复：CPLD和FPGA的主要区别是:EPLD是EEPROM的工艺,FPGA是SRAM的工艺,也就是说

EPLD内的程序掉电后不会丢失而FPGA掉电后会丢失每次上电需重新配置.但SRAM工艺使FPGA

容量越来越大.

fuzhuang问：nios 开发软件价格如何？

Horace答复：You can buy the Cyclone-Nios kit or Stratix-Nios kit, and we have

the special offer before end of June, 2003 Price = USD 495

xujin47问：对于初学者来说，怎样取得QUARTUS2完整版及“Nios”试验板（Demo board）

Bill Yuan答复：Quartus II 完整版本和NIOS试验板都需要购买，请和我们的代理商联系

holly问：cyclone支持ｖｈｄｌ吗？

robin答复：能够支持。

macray问：请问专家，一套标准的NIOS的评估套件要几个银子？

Horace答复：Cyclone-Nios Kit or Stratix-Nios Kit have a special offer before

End of June, 2003 Price = USD 495 per Kit

gmk54205问：在MAXPLUS 中怎样作才能对EPM7032S编程

Bill Yuan答复：在maxplus中可以用下载电缆直接对EPM7032S编程，只需要打开programme

r窗口，调入需要编程的文件即可

cxiang2001问：当前最热门用到的CPLD是什么？

ivan Li答复：Max 3000A& Max7000

fansr问：怎样能得到评估板的电原理图和印刷板图？？？？？？

Bill Yuan答复：我的会随评估板一起提供给客户电路原理图很印刷版图,所有的资料都在

配套的光盘中

Altera疑难问答

一. PLD/FPGA基本使用问题

1.PLD,CPLD,FPGA有何不同?

不同厂家的叫法不尽相同，PLD(Programmable Logic Device)是可编程逻辑器件的总称，

早期多EEPROM工艺，基于乘积项（Product Term）结构。 FPGA (Field Programmable

Gate Arry)是指现场可编程门阵列，最早由Xilinx公司发明。多为SRAM 工艺,基于查找表

（Look Up Table）结构，要外挂配置用的EPROM。 Xilinx把SRAM工艺,要外挂配置用的EPR

OM的PLD叫FPGA,把Flash工艺（类似EEPROM工艺）,乘积项结构的PLD叫CPLD; Altera把自己

的PLD产品:MAX系列（EEPROM工艺）,FLEX/ACEX/APEX系列（SRAM工艺）都叫作CPLD,即复杂

PLD(Complex PLD),由于FLEX/ACEX/APEX系列也是SRAM工艺,要外挂配置用的EPROM,用法和X

ilinx的FPGA一样，所以很多人把Altera的FELX/ACEX/APEX系列产品也叫做FPGA.

2. 我原来有一个74系列设计的电路，工作很正常，为什么原封不动集成到PLD中以后却不

能正常工作，是芯片有问题吗？

这是一个非常有代表性的问题。设计PLD/FPGA内部电路与设计74的分立电路是有区别的。

这个问题是由于电路中的毛刺造成的。电路布线长短不同造成延时不一致，有竞争冒险，

会产生毛刺。分立元件之间存在分布电容和电感可以滤掉这些毛刺，所以用分立元件设计

电路时，很少考虑竞争冒险和毛刺问题，但PLD/FPGA内部没有分布电容和电感，不可以滤

掉任何毛刺（哪怕只有1ns)。有些毛刺是可以忽略的，有些是致命的（如D触发器的clk,cl

r,PRN端）、。这些致命的毛刺将导致电路不能正常工作。这是设计FPGA和设计分立元件最

大的不同。可以通过修改电路减少有害毛刺。参见: 培训中心>培训资料> PLD设计技巧—

—消除组合逻辑产生的毛刺 和 PLD设计技巧——采用同步电路设计 ，根据经验，几乎所

有稳定性或可靠性问题都是由PLD内部电路设计不合理造成的，这一点要千万小心。

3. 如何将信号做一定延时？

当需要对某一信号作一段延时时，初学者往往在此信号后串接一些非门或其它门电路，此

方法在分离电路中是可行的。但在ＦＰＧＡ中，开发软件在综合设计时会将这些门当作冗

余逻辑去掉，达不到延时的效果。用ALTERA公司的MaxplusII开发ＦＰＧＡ时，可以通过插

入一些ＬＣＥＬＬ原语来产生一定的延时，但这样形成的延时在ＦＰＧＡ芯片中并不稳定

，会随温度等外部环境的改变而改变，因此并不提倡这样做。在此，可以用高频时钟来驱

动一移位寄存器，待延时信号作数据输入，按所需延时正确设置移位寄存器的级数，移位

寄存器的输出即为延时后的信号。此方法产生的延时信号与原信号比有误差，误差大小由

高频时钟的周期来决定。对于数据信号的延时，在输出端用数据时钟对延时后信号重新采

样，就可以消除误差。

4.什么是IP核或IP库? 有那些种类？

IP核是指：将一些在数字电路中常用但比较复杂的功能块，如FIR滤波器，SDRAM控制器，P

CI接口等等设计成可修改参数的模块，让其他用户可以直接调用这些模块，这样就大大减

轻了工程师的负担，避免重复劳动。随着CPLD/FPGA的规模越来越大，设计越来越复杂，使

用IP核是一个发展趋势。 不过目前大多数库是收费的，如您希望一个免费方案，请到本站

参考设计栏目里找一找。

5.如何设计3.3v,2.5v 等低电压PLD/FPGA的电源？

多用低压差线形稳压器(LDO)或采用开关电源，详细内容参见低电压PLD/FPGA的供电设计

6.CPLD/FPGA的宏单元是怎么定义？一个宏单元对应多少门？

宏单元（或逻辑单元）是PLD/FPGA的最基本单元，不同产品对这种基本单元的叫法不同，

如LE,MC,CLB,Slices等，但每个基本单元一般都包括两部分，一部分实现组合逻辑，另一

部分实现时序逻辑。各个厂家的定义可能不一样。对ALTERA的芯片，每个基本单元含一个

触发器；对Xilinx的部分芯片，每个基本单元单元含两个触发器。一般不用“门”的数量

衡量PLD/FPGA的大小，因为各家对门数的算法不一样，象ALTERA和Xilinx对门的计算结果

就差了一倍，推荐用触发器的多少来衡量芯片的大小。如10万门的Xilinx的XC2S100有1200

个slices，即含2400个触发器；5万门的ALTERA的1K50则含2880个LE，即2880个触发器。更

详细资料请浏览PLD/FPGA原理栏目