CrazyBingo

Avalon-MM____KEY_LED IP Design

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(1)verilog代码

/********************************************************************
* Module Name : Crazy_KEY_LED
* Author : Crazy Bingo
* Device : EP2C8Q208C8
* Version : Quartus II 10.1
* Date : 2011-3-2
* Description :
*********************************************************************/
module Crazy_KEY_LED
(
//Avalon Clock
input csi_clk,
input csi_rst_n,
//Avalon-MM
input avs_chipselect,
input [1:0] avs_address, //multiple of 4
// input [1:0] avs_byteenable_n, //1,2,4,8,16,54,128
input avs_write,
input [31:0] avs_writedata, //32bit cpu
input avs_read,
output [31:0] avs_readdata, //32bit cpu
//Avalon Conduit
input [1:0] coe_key_data,
output [1:0] coe_led_data // 2 bis led
);

//write led_data
reg [1:0] coe_led_data_r;
always @(posedge csi_clk or negedge csi_rst_n)
begin
if(!csi_rst_n)
coe_led_data_r <= 0;
else if (avs_chipselect && avs_write && (avs_address == 0))
coe_led_data_r <= avs_writedata[1:0];
end
assign coe_led_data = coe_led_data_r;

//read key_data
reg [1:0] avs_readdata_r;
always @(posedge csi_clk or negedge csi_rst_n)
begin
if(!csi_rst_n)
avs_readdata_r <= 0;
else if (avs_chipselect && avs_read && (avs_address == 1)) //for steady state
avs_readdata_r <= coe_key_data;
end
assign avs_readdata = avs_readdata_r;

endmodule

(2)SOPC导入ip




(3)建立Quartus 工程

module sram_test
(
//global clk
input clk,
input rst_n,
//sram interface
inout [15:0] sram_data,
output [18:0] sram_addr,
output sram_ce_n,
output sram_we_n,
output sram_oe_n,
output sram_ub_n,
output sram_lb_n,
//user interface
input [1:0] key_data,
output [1:0] led_data
);

sram_test_core sram_test_core_inst
(
.clk (clk),
.reset_n (rst_n),
.coe_SRAM_ADDR_from_the_sram (sram_addr),
.coe_SRAM_CE_N_from_the_sram (sram_ce_n),
.coe_SRAM_DQ_to_and_from_the_sram (sram_data),
.coe_SRAM_LB_N_from_the_sram (sram_lb_n),
.coe_SRAM_OE_N_from_the_sram (sram_oe_n),
.coe_SRAM_UB_N_from_the_sram (sram_ub_n),
.coe_SRAM_WE_N_from_the_sram (sram_we_n),
.coe_key_data_to_the_key_led_data (key_data),
.coe_led_data_from_the_key_led_data (led_data)
);

endmodule


(4)建立nios2 工程

//----------------------------------------------------------

文件"my_sopc.h"

#ifndef MY_SOPC_H_
#define MY_SOPC_H_

#include "alt_types.h"
#include "system.h"

#define CRAZY_KEY_LED_DATA
//---------------------------------------------------------
#ifdef CRAZY_KEY_LED_DATA
#define KEY_LED_DATA_ADDR (KEY_LED_DATA_BASE | (1<<31))
#define LED_DATA (*(volatile unsigned int*)(KEY_LED_DATA_ADDR + 0x00))
#define KEY_DATA (*(volatile unsigned int*)(KEY_LED_DATA_ADDR + 0x04))
#endif

//----------------------------------------------------------

文件 "nios2_main.v"

#include
#include "system.h"
#include "unistd.h"
#include "io.h"

#include "my_sopc.h"

alt_u8 key_scan(void)
{
alt_u8 key_value = KEY_DATA;
if(key_value == 3)
return 3;
else
{
if(KEY_DATA == key_value)
{
usleep(5000);
if(KEY_DATA == key_value)
{
// while(KEY_DATA != key_value);
// usleep(5000);
// while(KEY_DATA != key_value);
return key_value;
}
else
return 3;
}
else
return 3;
}
}
int main()
{
printf("Hello from Nios II!\n");
while(1)
{
LED_DATA = ~key_scan();
}
return 0;
}

run handware OK

注意:地址分配的一一对应

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