LinCoding

FPGA,Verilog中如何实现for循环

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/*----------------------------LinCoding-------------------------------*/

参考总结自Verilog那些事。。。

/* 单个for循环 */

for ( i=0; i<10; i++ )

{

Act++;

}

//1、时序实现

case ( i )

0:

begin

if ( x == C1 )

begin

x <= x + 1'b1;

Act <= Act + 1'b1;

end

if ( C1 == 10 - 1 )

begin

x <= 8'd0;

C1 <= 8'd0;

i <= i + 1'b1;

end

else

C1 <= C1 + 1'b1;

end

endcase

//2、步骤实现

case ( i )

0:

if ( x == 10 )

begin

x <= 8'd0;

i <= i + 1'b1;

end

else

begin

x <= x + 1'b1;

Act <= Act + 1'b1;

end

endcase




/* for循环嵌套 类型1 */

for ( x=0; x<10; x++ )

{

for ( y=0; y<10; y++ )

{

Act++;

}

}

//1、时序实现

case ( i )

0:

begin

if ( x == C1 )

begin

x <= x + 1'b1;

Act <= Act + 1'b1;

end

if ( C1 == 100-1 )

begin

x <= 0;

C1 <= 0;

i <= i + 1'b1;

end

else

C1 <= C1 + 1'b1;

end

endcase

//2、步骤实现

case ( i )

0:

if ( x == 100 )

begin

x <= 8'd0;

i <= i + 1'b1;

end

else

begin

x <= x + 1'b1;

Act <= Act + 1'b1;

end

endcase



/* for循环嵌套 类型2 */

for ( x=0; x<10; x++ )

{

for ( y=0; y<10; y++ )

{

Act1++;

Act2++;

}

}

//1、时序实现

case ( i )

0:

begin

if ( x == C1 )

begin

x <= x + 1'b1;

Act1 <= Act1 + 1'b1;

Act2 <= Act2 + 1'b1;

end

if ( C1 == 100-1 )

begin

x <= 0;

C1 <= 0;

i <= i + 1'b1;

end

else

C1 <= C1 + 1'b1;

end

endcase

//2、步骤实现

case ( i )

0:

if ( x == 100 )

begin

x <= 8'd0;

i <= i + 1'b1;

end

else

begin

x <= x + 1'b1;

Act1 <= Act1 + 1'b1;

Act2 <= Act2 + 1'b1;

end

endcase


/* for循环嵌套 类型3 */

for ( x=0; x<10; x++ )

{

Act1++;

for ( y=0; y<10; y++ )

{

Act2++;

}

}

//1、时序实现

case ( i )

0:

begin

if ( x == C1 )

begin

x <= x + 8'd10;

Act1 <= Act1 + 1'b1;

end

if ( y == C1 )

begin

y <= y + 1'b1;

Act2 <= Act2 + 1'b1;

end

if ( C1 == 100-1 )

begin

x <= 0;

y <= 0;

C1 <= 0;

i <= i + 1'b1;

end

else

C1 <= C1 + 1'b1;

end

endcase

//2、步骤实现

case ( i )

0:

if ( x == 10 )

begin

x <= 8'd0;

y <= 8'd0;

i <= i + 1'b1;

end

else if ( y == 10 )

begin

x <= x + 1'b1;

y <= 8'd0;

Act1 <= Act1 + 1'b1;

end

else

begin

y <= y + 1'b1;

Act2 <= Act2 + 1'b1;

end

endcase


/* for循环嵌套 类型4 */

for ( x=0; x<10; x++ )

{

Act1++;

for ( y=0; y<10; y++ )

{

Act2 = Act1;

}

}

//1、时序实现

case ( i )

0:

begin

if ( x == C1 )

begin

x <= x + 8'd10;

Act1 = Act1 + 1'b1; //使用阻塞赋值

end

if ( y == C1 )

begin

y <= y + 1'b1;

Act2 <= Act1;

end

if ( C1 == 100-1 )

begin

x <= 0;

y <= 0;

C1 <= 0;

i <= i + 1'b1;

end

else

C1 <= C1 + 1'b1;

end

//2、步骤实现

case ( i )

0:

if ( x == 10 )

begin

x <= 8'd0;

y <= 8'd0;

i <= i + 1'b1;

end

else if ( y == 10 )

begin

x <= x + 1'b1;

y <= 8'd0;

Act1 <= Act1 + 1'b1;

end

else

begin

y <= y + 1'b1;

Act2 <= Act1;

end

endcase



/* for循环嵌套 类型5 */

for ( x=0; x<10; x++ )

{

Act1 = Act2;

for ( y=0; y<10; y++ )

{

Act2++;

}

}

//1、时序实现

case ( i )

0:

begin

if ( x == C1 )

begin

x <= x + 8'd10;

Act1 <= Act2; //使用阻塞赋值

end

if ( y == C1 )

begin

y <= y + 1'b1;

Act2 = Act2 + 1'b1;

end

if ( C1 == 100-1 )

begin

x <= 0;

y <= 0;

C1 <= 0;

i <= i + 1'b1;

end

else

C1 <= C1 + 1'b1;

end

//2、步骤实现

case ( i )

0:

if ( x == 10 )

begin

x <= 8'd0;

y <= 8'd0;

i <= i + 1'b1;

end

else if ( y == 10 )

begin

x <= x + 1'b1;

y <= 8'd0;

Act1 <= Act2;

end

else

begin

y <= y + 1'b1;

Act2 <= Act2 + 1'b1;

end

endcase



/* for循环嵌套 类型6,此法为类型4,5,6中最好的 */

for ( x=0; x<10; x++ )

{

Act2++;

for ( y=0; y<10; y++ )

{

Act1 = Act2;

}

}

case ( i )

0:

begin

if ( x == C1 )

begin

x <= x + 8'd10;

Act2 <= ( x != 101 - 1 ) ? Act2 + 1'b1 : Act2;

end

if ( y + 1 == C1 )

begin

y <= y + 1'b1;

Act1 <= Act2;

end

if ( C1 === 101 - 1 )

begin

x <= 8'd0;

y <= 8'd0;

i <= i + 1'b1;

end

else

C1 <= C1 + 1'b1;

end

endcase


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